about summary refs log tree commit diff
diff options
context:
space:
mode:
authorkennytm <kennytm@gmail.com>2019-03-24 15:32:45 +0800
committerGitHub <noreply@github.com>2019-03-24 15:32:45 +0800
commit48dc8efc8595d397b3820a0784f0dbe553c3fb27 (patch)
treeb2e32713e5026bcba10a6834970533ba4159c5a2
parent6c5e1d151a2526a8f597150b0ec01e22f550a002 (diff)
parent830c98d7fa4da9381d3ee9c8b918bc5dff11c378 (diff)
downloadrust-48dc8efc8595d397b3820a0784f0dbe553c3fb27.tar.gz
rust-48dc8efc8595d397b3820a0784f0dbe553c3fb27.zip
Rollup merge of #59239 - gnzlbg:fix_spin_loop, r=nagisa
Remove inline assembly from hint::spin_loop

This PR removes the inline assembly which was not required since these
instructions are available in core::arch, and extends support of
the spin_loop hint to arm targets with the v6 feature which also
support the yield instruction.
-rw-r--r--src/libcore/hint.rs31
1 files changed, 25 insertions, 6 deletions
diff --git a/src/libcore/hint.rs b/src/libcore/hint.rs
index 89de5c1bc8a..b2f82ef0d17 100644
--- a/src/libcore/hint.rs
+++ b/src/libcore/hint.rs
@@ -62,13 +62,32 @@ pub unsafe fn unreachable_unchecked() -> ! {
 #[inline]
 #[unstable(feature = "renamed_spin_loop", issue = "55002")]
 pub fn spin_loop() {
-    #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
-    unsafe {
-        asm!("pause" ::: "memory" : "volatile");
+    #[cfg(
+        all(
+            any(target_arch = "x86", target_arch = "x86_64"),
+            target_feature = "sse2"
+        )
+    )] {
+        #[cfg(target_arch = "x86")] {
+            unsafe { crate::arch::x86::_mm_pause() };
+        }
+
+        #[cfg(target_arch = "x86_64")] {
+            unsafe { crate::arch::x86_64::_mm_pause() };
+        }
     }
 
-    #[cfg(target_arch = "aarch64")]
-    unsafe {
-        asm!("yield" ::: "memory" : "volatile");
+    #[cfg(
+        any(
+            target_arch = "aarch64",
+            all(target_arch = "arm", target_feature = "v6")
+        )
+    )] {
+        #[cfg(target_arch = "aarch64")] {
+            unsafe { crate::arch::aarch64::__yield() };
+        }
+        #[cfg(target_arch = "arm")] {
+            unsafe { crate::arch::arm::__yield() };
+        }
     }
 }