diff options
| author | Ruud van Asseldonk <ruuda@google.com> | 2016-03-08 22:36:54 +0100 |
|---|---|---|
| committer | Ruud van Asseldonk <ruuda@google.com> | 2016-03-09 01:18:46 +0100 |
| commit | 51b5300b3fc83b445cd1e410be4b7d123f10472e (patch) | |
| tree | 3d700644680e9669b68518e1fbade39800f4c965 | |
| parent | 37efeae8866c3c4d9827d0ca271b8e27f731c3e1 (diff) | |
| download | rust-51b5300b3fc83b445cd1e410be4b7d123f10472e.tar.gz rust-51b5300b3fc83b445cd1e410be4b7d123f10472e.zip | |
Define AVX conversion intrinsics
This defines the following intrinsics: * `_mm256_cvtepi32_pd` * `_mm256_cvtepi32_ps` * `_mm256_cvtpd_epi32` * `_mm256_cvtpd_ps` * `_mm256_cvtps_epi32` * `_mm256_cvtps_pd` * `_mm256_cvttpd_epi32` * `_mm256_cvttps_epi32` Intel reference: https://software.intel.com/en-us/node/514130.
| -rw-r--r-- | src/etc/platform-intrinsics/x86/avx.json | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/etc/platform-intrinsics/x86/avx.json b/src/etc/platform-intrinsics/x86/avx.json index 981838536b2..08524fbd6dd 100644 --- a/src/etc/platform-intrinsics/x86/avx.json +++ b/src/etc/platform-intrinsics/x86/avx.json @@ -16,6 +16,62 @@ "args": ["s8SPc"] }, { + "intrinsic": "256_cvtepi32_pd", + "width": [256], + "llvm": "cvtdq2.pd.256", + "ret": "f64", + "args": ["s32h"] + }, + { + "intrinsic": "256_cvtepi32_ps", + "width": [256], + "llvm": "cvtdq2.ps.256", + "ret": "f32", + "args": ["s32"] + }, + { + "intrinsic": "256_cvtpd_epi32", + "width": [256], + "llvm": "cvt.pd2dq.256", + "ret": "s32h", + "args": ["f64"] + }, + { + "intrinsic": "256_cvtpd_ps", + "width": [256], + "llvm": "cvt.pd2.ps.256", + "ret": "f32h", + "args": ["f64"] + }, + { + "intrinsic": "256_cvtps_epi32", + "width": [256], + "llvm": "cvt.ps2dq.256", + "ret": "s32", + "args": ["f32"] + }, + { + "intrinsic": "256_cvtps_pd", + "width": [256], + "llvm": "cvt.ps2.pd.256", + "ret": "f64", + "args": ["f32h"] + }, + { + "intrinsic": "256_cvttpd_epi32", + "width": [256], + "llvm": "cvtt.pd2dq.256", + "ret": "s32h", + "args": ["f64"] + }, + { + "intrinsic": "256_cvttps_epi32", + "width": [256], + "llvm": "cvtt.ps2dq.256", + "ret": "s32", + "args": ["f32"] + }, + { "intrinsic": "256_dp_ps", "width": [256], "llvm": "dp.ps.256", |
