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| author | Lokathor <zefria@gmail.com> | 2021-11-09 13:30:30 -0700 |
|---|---|---|
| committer | Lokathor <zefria@gmail.com> | 2021-11-09 13:30:30 -0700 |
| commit | 5c396e4b99592a245c86b653710c9aeef43e3b44 (patch) | |
| tree | 435a951372903173c4ca83e59c0867c3f56789d2 | |
| parent | 07acdb48a0e0b22d08a45e3ced0378e0027b40eb (diff) | |
| download | rust-5c396e4b99592a245c86b653710c9aeef43e3b44.tar.gz rust-5c396e4b99592a245c86b653710c9aeef43e3b44.zip | |
adjust documented register constraints to match https://llvm.org/docs/LangRef.html#supported-constraint-code-list
| -rw-r--r-- | src/doc/unstable-book/src/library-features/asm.md | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/doc/unstable-book/src/library-features/asm.md b/src/doc/unstable-book/src/library-features/asm.md index 84fc6dcc339..b7e10734c57 100644 --- a/src/doc/unstable-book/src/library-features/asm.md +++ b/src/doc/unstable-book/src/library-features/asm.md @@ -562,9 +562,12 @@ Here is the list of currently supported register classes: | AArch64 | `vreg` | `v[0-31]` | `w` | | AArch64 | `vreg_low16` | `v[0-15]` | `x` | | AArch64 | `preg` | `p[0-15]`, `ffr` | Only clobbers | -| ARM | `reg` | `r[0-12]`, `r14` | `r` | -| ARM (Thumb) | `reg_thumb` | `r[0-r7]` | `l` | +| ARM (ARM) | `reg` | `r[0-12]`, `r14` | `r` | +| ARM (Thumb2) | `reg` | `r[0-12]`, `r14` | `r` | +| ARM (Thumb1) | `reg` | `r[0-r7]` | `r` | | ARM (ARM) | `reg_thumb` | `r[0-r12]`, `r14` | `l` | +| ARM (Thumb2) | `reg_thumb` | `r[0-r7]` | `l` | +| ARM (Thumb1) | `reg_thumb` | `r[0-r7]` | `l` | | ARM | `sreg` | `s[0-31]` | `t` | | ARM | `sreg_low16` | `s[0-15]` | `x` | | ARM | `dreg` | `d[0-31]` | `w` | |