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authorbors <bors@rust-lang.org>2022-08-25 18:17:42 +0000
committerbors <bors@rust-lang.org>2022-08-25 18:17:42 +0000
commit7480389611f9d04bd34adf41a2b3029be4eb815e (patch)
tree2e56280a7792b1bb66353028bba8c9a7571cf1ed
parent4d45b0745ab227feb9000bc15713ade4b99241ea (diff)
parent5f4d23dd143295bc637410b31e29b405806c1622 (diff)
downloadrust-7480389611f9d04bd34adf41a2b3029be4eb815e.tar.gz
rust-7480389611f9d04bd34adf41a2b3029be4eb815e.zip
Auto merge of #100911 - tmiasko:update-stdarch, r=Amanieu
Update stdarch submodule

Changes from stdarch:

* Fix links in documentation of cmpxchg16b
* Use load intrinsic and loop for intrinsic-test programs. Add --release flag back to intrinsic-test programs.
* Properly fix vext intrinsic tests
* Replace some calls to `pointer::offset` with `add` and `sub`
* Allow internal use of stdsimd from detect_feature
* fix target name in contributing.md
* Tweak constant for ARM vext instruction tests
* Use `llvm.ppc.altivec.lvx` intrinsic for `vec_ld`
*  Adding doc links for arm neon intrinsics
* Adding doc links for arm crypto and aes intrinsics
* Remove instruction tests for `__mmask*` intrinsics
* Update ubuntu 21.10 docker containers to 22.04
* Adding documentation links for arm crc32 intrinsics
* Remove restrictions on compare-exchange memory ordering.
* Fix a typo in the document.
* Allow mapping a runtime feature to a set of target_features
* Update atomic intrinsics
* Fully qualify recursive macro calls
* Ensure the neon vector aggregates like `float32x4x4_t` are `#[repr(C)]`
* Remove useless conditional compilation
* Fix ARM vbsl* NEON intrinsics

r? `@Amanieu`
-rw-r--r--library/core/src/intrinsics.rs21
-rw-r--r--library/panic_unwind/src/seh.rs15
m---------library/stdarch0
3 files changed, 9 insertions, 27 deletions
diff --git a/library/core/src/intrinsics.rs b/library/core/src/intrinsics.rs
index 441d2382686..f27ac24fded 100644
--- a/library/core/src/intrinsics.rs
+++ b/library/core/src/intrinsics.rs
@@ -737,28 +737,7 @@ extern "rust-intrinsic" {
     /// [`atomic::compiler_fence`] by passing [`Ordering::AcqRel`]
     /// as the `order`.
     pub fn atomic_singlethreadfence_acqrel();
-}
-
-// These have been renamed.
-//
-// These are the aliases for the old names.
-// To be removed when stdarch and panic_unwind have been updated.
-mod atomics {
-    pub use super::atomic_cxchg_acqrel_acquire as atomic_cxchg_acqrel;
-    pub use super::atomic_cxchg_acqrel_relaxed as atomic_cxchg_acqrel_failrelaxed;
-    pub use super::atomic_cxchg_acquire_acquire as atomic_cxchg_acq;
-    pub use super::atomic_cxchg_acquire_relaxed as atomic_cxchg_acq_failrelaxed;
-    pub use super::atomic_cxchg_relaxed_relaxed as atomic_cxchg_relaxed;
-    pub use super::atomic_cxchg_release_relaxed as atomic_cxchg_rel;
-    pub use super::atomic_cxchg_seqcst_acquire as atomic_cxchg_failacq;
-    pub use super::atomic_cxchg_seqcst_relaxed as atomic_cxchg_failrelaxed;
-    pub use super::atomic_cxchg_seqcst_seqcst as atomic_cxchg;
-    pub use super::atomic_store_seqcst as atomic_store;
-}
 
-pub use atomics::*;
-
-extern "rust-intrinsic" {
     /// The `prefetch` intrinsic is a hint to the code generator to insert a prefetch instruction
     /// if supported; otherwise, it is a no-op.
     /// Prefetches have no effect on the behavior of the program but can change its performance
diff --git a/library/panic_unwind/src/seh.rs b/library/panic_unwind/src/seh.rs
index 9f1eb411ff6..b243333c48e 100644
--- a/library/panic_unwind/src/seh.rs
+++ b/library/panic_unwind/src/seh.rs
@@ -256,7 +256,7 @@ cfg_if::cfg_if! {
 }
 
 pub unsafe fn panic(data: Box<dyn Any + Send>) -> u32 {
-    use core::intrinsics::atomic_store;
+    use core::intrinsics::atomic_store_seqcst;
 
     // _CxxThrowException executes entirely on this stack frame, so there's no
     // need to otherwise transfer `data` to the heap. We just pass a stack
@@ -288,20 +288,23 @@ pub unsafe fn panic(data: Box<dyn Any + Send>) -> u32 {
     //
     // In any case, we basically need to do something like this until we can
     // express more operations in statics (and we may never be able to).
-    atomic_store(&mut THROW_INFO.pmfnUnwind as *mut _ as *mut u32, ptr!(exception_cleanup) as u32);
-    atomic_store(
+    atomic_store_seqcst(
+        &mut THROW_INFO.pmfnUnwind as *mut _ as *mut u32,
+        ptr!(exception_cleanup) as u32,
+    );
+    atomic_store_seqcst(
         &mut THROW_INFO.pCatchableTypeArray as *mut _ as *mut u32,
         ptr!(&CATCHABLE_TYPE_ARRAY as *const _) as u32,
     );
-    atomic_store(
+    atomic_store_seqcst(
         &mut CATCHABLE_TYPE_ARRAY.arrayOfCatchableTypes[0] as *mut _ as *mut u32,
         ptr!(&CATCHABLE_TYPE as *const _) as u32,
     );
-    atomic_store(
+    atomic_store_seqcst(
         &mut CATCHABLE_TYPE.pType as *mut _ as *mut u32,
         ptr!(&TYPE_DESCRIPTOR as *const _) as u32,
     );
-    atomic_store(
+    atomic_store_seqcst(
         &mut CATCHABLE_TYPE.copyFunction as *mut _ as *mut u32,
         ptr!(exception_copy) as u32,
     );
diff --git a/library/stdarch b/library/stdarch
-Subproject 28335054b1f417175ab5005cf1d9cf793773793
+Subproject 42df7394d38bc7b945116ea3ad8a7cbcd1db50a