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| author | bors <bors@rust-lang.org> | 2025-06-07 12:25:59 +0000 |
|---|---|---|
| committer | bors <bors@rust-lang.org> | 2025-06-07 12:25:59 +0000 |
| commit | 83be7a8960b8d005454192105249a7f44886ca7f (patch) | |
| tree | 62a8ddc43d25537d4658425fa5414d60e1327f40 | |
| parent | 363003951cd20e725990795dc82d4bed64c0cf53 (diff) | |
| parent | b97136c817c989f37baca1191a07828346251a64 (diff) | |
| download | rust-83be7a8960b8d005454192105249a7f44886ca7f.tar.gz rust-83be7a8960b8d005454192105249a7f44886ca7f.zip | |
Auto merge of #141964 - sayantn:update-stdarch, r=Amanieu
Update stdarch submodule Updates the stdarch submodule. ## Merged PRs - rust-lang/stdarch#1797 - rust-lang/stdarch#1758 - rust-lang/stdarch#1798 - rust-lang/stdarch#1811 - rust-lang/stdarch#1810 - rust-lang/stdarch#1807 - rust-lang/stdarch#1806 - rust-lang/stdarch#1812 - rust-lang/stdarch#1795 - rust-lang/stdarch#1796 - rust-lang/stdarch#1813 - rust-lang/stdarch#1816 - rust-lang/stdarch#1818 - rust-lang/stdarch#1820 - rust-lang/stdarch#1819 r? `@Amanieu` `@rustbot` label T-libs-api Closes rust-lang/rust#111137
| -rw-r--r-- | example/neon.rs | 2 | ||||
| -rw-r--r-- | src/intrinsics/llvm.rs | 8 | ||||
| -rw-r--r-- | src/intrinsics/llvm_aarch64.rs | 8 |
3 files changed, 9 insertions, 9 deletions
diff --git a/example/neon.rs b/example/neon.rs index 69ce17d3d75..704f866e2c4 100644 --- a/example/neon.rs +++ b/example/neon.rs @@ -233,7 +233,7 @@ unsafe fn test_vaddvq_f32() { #[cfg(target_arch = "aarch64")] unsafe fn test_vrndnq_f32() { - // AArch64 llvm intrinsic: llvm.aarch64.neon.frintn.v4f32 + // llvm intrinsic: llvm.roundeven.v4f32 let a = f32x4::from([0.1, -1.9, 4.5, 5.5]); let e = f32x4::from([0., -2., 4., 6.]); let r: f32x4 = transmute(vrndnq_f32(transmute(a))); diff --git a/src/intrinsics/llvm.rs b/src/intrinsics/llvm.rs index 99a5518d0b6..2dee9176936 100644 --- a/src/intrinsics/llvm.rs +++ b/src/intrinsics/llvm.rs @@ -62,6 +62,14 @@ pub(crate) fn codegen_llvm_intrinsic_call<'tcx>( }); } + _ if intrinsic.starts_with("llvm.roundeven.v") => { + intrinsic_args!(fx, args => (v); intrinsic); + + simd_for_each_lane(fx, v, ret, &|fx, _lane_ty, _res_lane_ty, lane| { + fx.bcx.ins().nearest(lane) + }); + } + _ => { fx.tcx .dcx() diff --git a/src/intrinsics/llvm_aarch64.rs b/src/intrinsics/llvm_aarch64.rs index c22f2a7b873..3cd7ebb88f4 100644 --- a/src/intrinsics/llvm_aarch64.rs +++ b/src/intrinsics/llvm_aarch64.rs @@ -264,14 +264,6 @@ pub(super) fn codegen_aarch64_llvm_intrinsic_call<'tcx>( simd_reduce(fx, v, None, ret, &|fx, _ty, a, b| fx.bcx.ins().fadd(a, b)); } - _ if intrinsic.starts_with("llvm.aarch64.neon.frintn.v") => { - intrinsic_args!(fx, args => (v); intrinsic); - - simd_for_each_lane(fx, v, ret, &|fx, _lane_ty, _res_lane_ty, lane| { - fx.bcx.ins().nearest(lane) - }); - } - _ if intrinsic.starts_with("llvm.aarch64.neon.smaxv.i") => { intrinsic_args!(fx, args => (v); intrinsic); |