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| author | cui fliter <imcusg@gmail.com> | 2023-08-23 21:36:45 +0800 |
|---|---|---|
| committer | cui fliter <imcusg@gmail.com> | 2023-08-25 15:45:41 +0800 |
| commit | 9c3f44f922adaf1a5797c5e5e66414369ad5ffc8 (patch) | |
| tree | 8633cf7ce6708d36ea65f23443f088dadcd7eb5f | |
| parent | 3475fa74e118e2eaee8420a7898177f6387e17b4 (diff) | |
| download | rust-9c3f44f922adaf1a5797c5e5e66414369ad5ffc8.tar.gz rust-9c3f44f922adaf1a5797c5e5e66414369ad5ffc8.zip | |
use the correct link
Signed-off-by: cui fliter <imcusg@gmail.com>
| -rw-r--r-- | library/core/src/convert/num.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/library/core/src/convert/num.rs b/library/core/src/convert/num.rs index 56ab63be27d..b048b513592 100644 --- a/library/core/src/convert/num.rs +++ b/library/core/src/convert/num.rs @@ -142,9 +142,9 @@ impl_from! { i16, isize, #[stable(feature = "lossless_iusize_conv", since = "1.2 // RISC-V defines the possibility of a 128-bit address space (RV128). -// CHERI proposes 256-bit “capabilities”. Unclear if this would be relevant to usize/isize. +// CHERI proposes 128-bit “capabilities”. Unclear if this would be relevant to usize/isize. // https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/20171017a-cheri-poster.pdf -// https://www.csl.sri.com/users/neumann/2012resolve-cheri.pdf +// https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-951.pdf // Note: integers can only be represented with full precision in a float if // they fit in the significand, which is 24 bits in f32 and 53 bits in f64. |