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| author | bjorn3 <bjorn3@users.noreply.github.com> | 2020-03-29 12:02:00 +0200 |
|---|---|---|
| committer | bjorn3 <bjorn3@users.noreply.github.com> | 2020-07-25 12:29:55 +0200 |
| commit | e8f1c5c53ab10a72f17ca0816b5890377ba5fc9c (patch) | |
| tree | cf07af13b29eca3d1b4016c0cad4e52001d36fbd | |
| parent | 67028cee5177aa5e5f9300114c9a8449258adb3a (diff) | |
| download | rust-e8f1c5c53ab10a72f17ca0816b5890377ba5fc9c.tar.gz rust-e8f1c5c53ab10a72f17ca0816b5890377ba5fc9c.zip | |
Don't forbid i64x2 as simd type
| -rw-r--r-- | src/intrinsics/mod.rs | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/intrinsics/mod.rs b/src/intrinsics/mod.rs index ea7326edc04..546864fc477 100644 --- a/src/intrinsics/mod.rs +++ b/src/intrinsics/mod.rs @@ -182,10 +182,8 @@ pub(crate) fn clif_vector_type<'tcx>(tcx: TyCtxt<'tcx>, layout: TyAndLayout<'tcx }; match scalar_to_clif_type(tcx, element).by(u16::try_from(count).unwrap()) { - // Cranelift currently only implements icmp for 128bit vectors. While 64bit lanes are - // supported, this needs either the `use_sse41_simd` or `use_sse42_simd` target flag - // to be enabled. - Some(vector_ty) if vector_ty.bits() == 128 && vector_ty.lane_type() != types::I64 => Some(vector_ty), + // Cranelift currently only implements icmp for 128bit vectors. + Some(vector_ty) if vector_ty.bits() == 128 => Some(vector_ty), _ => None, } } |