arm target docs: collapsed eabi and eabihf into one

7 files changed, 56 insertions, 223 deletions

diff --git a/src/doc/rustc/src/SUMMARY.md b/src/doc/rustc/src/SUMMARY.md
index 9dd68555bbe..a3de28f8015 100644
--- a/src/doc/rustc/src/SUMMARY.md
+++ b/src/doc/rustc/src/SUMMARY.md
@@ -57,11 +57,9 @@
     - [sparc-unknown-none-elf](./platform-support/sparc-unknown-none-elf.md)
     - [thumbv6m-none-eabi](./platform-support/thumbv6m-none-eabi.md)
     - [thumbv7m-none-eabi](./platform-support/thumbv7m-none-eabi.md)
-    - [thumbv7em-none-eabi](./platform-support/thumbv7em-none-eabi.md)
-    - [thumbv7em-none-eabihf](./platform-support/thumbv7em-none-eabihf.md)
+    - [thumbv7em-none-eabi\*](./platform-support/thumbv7em-none-eabi.md)
     - [thumbv8m.base-none-eabi](./platform-support/thumbv8m.base-none-eabi.md)
-    - [thumbv8m.main-none-eabi](./platform-support/thumbv8m.main-none-eabi.md)
-    - [thumbv8m.main-none-eabihf](./platform-support/thumbv8m.main-none-eabihf.md)
+    - [thumbv8m.main-none-eabi\*](./platform-support/thumbv8m.main-none-eabi.md)
     - [*-pc-windows-gnullvm](platform-support/pc-windows-gnullvm.md)
     - [\*-nto-qnx-\*](platform-support/nto-qnx.md)
     - [*-unikraft-linux-musl](platform-support/unikraft-linux-musl.md)
diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md
index 526b5a59789..cdab3d4401e 100644
--- a/src/doc/rustc/src/platform-support.md
+++ b/src/doc/rustc/src/platform-support.md
@@ -180,13 +180,13 @@ target | std | notes
 `sparcv9-sun-solaris` | ✓ | SPARC Solaris 11, illumos
 [`thumbv6m-none-eabi`](platform-support/thumbv6m-none-eabi.md) | * | Bare ARMv6-M
 [`thumbv7em-none-eabi`](platform-support/thumbv7em-none-eabi.md) | * | Bare ARMv7E-M
-[`thumbv7em-none-eabihf`](platform-support/thumbv7em-none-eabihf.md) | * | Bare ARMV7E-M, hardfloat
+[`thumbv7em-none-eabihf`](platform-support/thumbv7em-none-eabi.md) | * | Bare ARMV7E-M, hardfloat
 [`thumbv7m-none-eabi`](platform-support/thumbv7m-none-eabi.md) | * | Bare ARMv7-M
 [`thumbv7neon-linux-androideabi`](platform-support/android.md) | ✓ | Thumb2-mode ARMv7-A Android with NEON
 `thumbv7neon-unknown-linux-gnueabihf` | ✓ | Thumb2-mode ARMv7-A Linux with NEON (kernel 4.4, glibc 2.23)
 [`thumbv8m.base-none-eabi`](platform-support/thumbv8m.base-none-eabi.md) | * | Bare ARMv8-M Baseline
 [`thumbv8m.main-none-eabi`](platform-support/thumbv8m.main-none-eabi.md) | * | Bare ARMv8-M Mainline
-[`thumbv8m.main-none-eabihf`](platform-support/thumbv8m.main-none-eabihf.md) | * | Bare ARMv8-M Mainline, hardfloat
+[`thumbv8m.main-none-eabihf`](platform-support/thumbv8m.main-none-eabi.md) | * | Bare ARMv8-M Mainline, hardfloat
 `wasm32-unknown-emscripten` | ✓ | WebAssembly via Emscripten
 `wasm32-unknown-unknown` | ✓ | WebAssembly
 `wasm32-wasi` | ✓ | WebAssembly with WASI (undergoing a [rename to `wasm32-wasip1`][wasi-rename])
diff --git a/src/doc/rustc/src/platform-support/arm-none-eabi.md b/src/doc/rustc/src/platform-support/arm-none-eabi.md
index 55d2f50b762..64ae6017238 100644
--- a/src/doc/rustc/src/platform-support/arm-none-eabi.md
+++ b/src/doc/rustc/src/platform-support/arm-none-eabi.md
@@ -10,9 +10,9 @@
 - Arm M-Profile Architectures
   - [`thumbv6m-none-eabi`](thumbv6m-none-eabi.md)
   - [`thumbv7m-none-eabi`](thumbv7m-none-eabi.md)
-  - [`thumbv7em-none-eabi`](thumbv7em-none-eabi.md) and [`thumbv7em-none-eabihf`](thumbv7em-none-eabihf.md)
+  - [`thumbv7em-none-eabi` and `thumbv7em-none-eabihf`](thumbv7em-none-eabi.md)
   - [`thumbv8m.base-none-eabi`](thumbv8m.base-none-eabi.md)
-  - [`thumbv8m.main-none-eabi`](thumbv8m.main-none-eabi.md) and [`thumbv8m.main-none-eabihf`](thumbv8m.main-none-eabihf.md)
+  - [`thumbv8m.main-none-eabi` and `thumbv8m.main-none-eabihf`](thumbv8m.main-none-eabi.md)
 - *Legacy* Arm Architectures
   - None
 
diff --git a/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md b/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md
index 78a431fec93..698c8ae7a65 100644
--- a/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md
+++ b/src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md
@@ -1,4 +1,4 @@
-# `thumbv7em-none-eabi`
+# `thumbv7em-none-eabi` and `thumbv7em-none-eabihf`
 
 **Tier: 2**
 
@@ -11,14 +11,8 @@ Processors in this family include the:
 * [Arm Cortex-M7][cortex-m7] and Arm Cortex-M7F
 
 See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
-`arm-none-eabi` targets.
-
-This target uses the soft-float ABI: functions which take `f32` or `f64` as
-arguments will have those values packed into integer registers. This target
-therefore does not require the use of an FPU (which is optional on Cortex-M4 and
-Cortex-M7), but an FPU can be optionally enabled if desired. See also the
-hard-float ABI version of this target
-[`thumbv7em-none-eabihf`](thumbv7em-none-eabihf.md).
+`arm-none-eabi` targets, in particular the difference between the `eabi` and
+`eabihf` ABI.
 
 [t32-isa]: https://developer.arm.com/Architectures/T32%20Instruction%20Set%20Architecture
 [ARMv7E-M]: https://developer.arm.com/documentation/ddi0403/latest/
@@ -36,16 +30,26 @@ See [the bare-metal Arm
 docs](arm-none-eabi.md#target-cpu-and-target-feature-options) for details on how
 to use these flags.
 
-### Table of supported CPUs
+### Table of supported CPUs for `thumbv7em-none-eabi`
 
 | CPU        | FPU | DSP | Target CPU  | Target Features |
 | ---------- | --- | --- | ----------- | --------------- |
+| Any        | No  | Yes | None        | None            |
 | Cortex-M4  | No  | Yes | `cortex-m4` | `+soft-float`   |
 | Cortex-M4F | SP  | Yes | `cortex-m4` | None            |
 | Cortex-M7  | No  | Yes | `cortex-m7` | `+soft-float`   |
 | Cortex-M7F | SP  | Yes | `cortex-m7` | `-fp64`         |
 | Cortex-M7F | DP  | Yes | `cortex-m7` | None            |
 
+### Table of supported CPUs for `thumbv7em-none-eabihf`
+
+| CPU        | FPU | DSP | Target CPU  | Target Features |
+| ---------- | --- | --- | ----------- | --------------- |
+| Any        | SP  | Yes | None        | None            |
+| Cortex-M4F | SP  | Yes | `cortex-m4` | None            |
+| Cortex-M7F | SP  | Yes | `cortex-m7` | `-fp64`         |
+| Cortex-M7F | DP  | Yes | `cortex-m7` | None            |
+
 ### Arm Cortex-M4 and Arm Cortex-M4F
 
 The target CPU is `cortex-m4`.
@@ -55,7 +59,7 @@ The target CPU is `cortex-m4`.
   * enabled by default with this *target*
 * Cortex-M4F has a single precision FPU
   * support is enabled by default with this *target-cpu*
-  * disable support using the `+soft-float` feature
+  * disable support using the `+soft-float` feature (`eabi` only)
 
 ### Arm Cortex-M7 and Arm Cortex-M7F
 
@@ -67,4 +71,4 @@ The target CPU is `cortex-m7`.
 * Cortex-M7F have either a single-precision or double-precision FPU
   * double-precision support is enabled by default with this *target-cpu*
     * opt-out by using the `-f64` *target-feature*
-  * disable support entirely using the `+soft-float` feature
+  * disable support entirely using the `+soft-float` feature (`eabi` only)
diff --git a/src/doc/rustc/src/platform-support/thumbv7em-none-eabihf.md b/src/doc/rustc/src/platform-support/thumbv7em-none-eabihf.md
deleted file mode 100644
index d4c93e3197c..00000000000
--- a/src/doc/rustc/src/platform-support/thumbv7em-none-eabihf.md
+++ /dev/null
@@ -1,67 +0,0 @@
-# `thumbv7em-none-eabihf`
-
-**Tier: 2**
-
-Bare-metal target for CPUs in the [ARMv7E-M] architecture family that have an
-FPU, supporting a subset of the [T32 ISA][t32-isa].
-
-Processors in this family include the:
-
-* [Arm Cortex-M4F][cortex-m4]
-* [Arm Cortex-M7F][cortex-m7]
-
-See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
-`arm-none-eabi` targets.
-
-This target uses the hard-float ABI: functions which take `f32` or `f64` as
-arguments will have them passed via FPU registers. This target therefore
-requires the use of an FPU (which is optional on Cortex-M4 and Cortex-M7). See
-also the soft-float ABI version of this target
-[`thumbv7em-none-eabi`](thumbv7em-none-eabi.md).
-
-[t32-isa]: https://developer.arm.com/Architectures/T32%20Instruction%20Set%20Architecture
-[ARMv7E-M]: https://developer.arm.com/documentation/ddi0403/latest/
-[cortex-m4]: https://developer.arm.com/Processors/Cortex-M4
-[cortex-m7]: https://developer.arm.com/Processors/Cortex-M7
-
-## Target maintainers
-
-* [Rust Embedded Devices Working Group Cortex-M
-  Team](https://github.com/rust-embedded), `cortex-m@teams.rust-embedded.org`
-
-## Target CPU and Target Feature options
-
-See [the bare-metal Arm
-docs](arm-none-eabi.md#target-cpu-and-target-feature-options) for details on how
-to use these flags.
-
-### Table of supported CPUs
-
-| CPU        | FPU | DSP | Target CPU  | Target Features |
-| ---------- | --- | --- | ----------- | --------------- |
-| Cortex-M4F | SP  | Yes | `cortex-m4` | None            |
-| Cortex-M7F | SP  | Yes | `cortex-m7` | `-fp64`         |
-| Cortex-M7F | DP  | Yes | `cortex-m7` | None            |
-
-### Arm Cortex-M4 and Arm Cortex-M4F
-
-The target CPU is `cortex-m4`.
-
-* All Cortex-M4 have DSP extensions
-  * support is controlled by the `dsp` *target-feature*
-  * enabled by default with this *target-cpu*
-* Cortex-M4F has a single precision FPU
-  * support is enabled by default with this *target*
-  * support is required when using the hard-float ABI
-
-### Arm Cortex-M7 and Arm Cortex-M7F
-
-The target CPU is `cortex-m7`.
-
-* All Cortex-M7 have DSP extensions
-  * support is controlled by the `dsp` *target-feature*
-  * enabled by default with this *target-cpu*
-* Cortex-M7F have either a single-precision or double-precision FPU
-  * single precision support is enabled by default with this *target*
-  * double-precision support is enabled by default with this *target-cpu*
-    * opt-out by using the `-f64` *target-feature*
diff --git a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md
index cbac897390e..9541e1d582c 100644
--- a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md
+++ b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md
@@ -1,4 +1,4 @@
-# `thumbv8m.main-none-eabi`
+# `thumbv8m.main-none-eabi` and `thumbv8m.main-none-eabihf`
 
 **Tier: 2**
 
@@ -13,14 +13,8 @@ Processors in this family include the:
 * [Arm Cortex-M85][cortex-m85]
 
 See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
-`arm-none-eabi` targets.
-
-This target uses the soft-float ABI: functions which take `f32` or `f64` as
-arguments will have those values packed into integer registers. This target
-therefore does not require the use of an FPU (which is optional on Cortex-M33,
-Cortex-M55 and Cortex-M85), but an FPU can be optionally enabled if desired. See
-also the hard-float ABI version of this target
-[`thumbv8m.main-none-eabihf`](thumbv7em-none-eabihf.md).
+`arm-none-eabi` targets, in particular the difference between the `eabi` and
+`eabihf` ABI.
 
 [t32-isa]: https://developer.arm.com/Architectures/T32%20Instruction%20Set%20Architecture
 [ARMv8-M]: https://developer.arm.com/documentation/ddi0553/latest/
@@ -40,18 +34,19 @@ See [the bare-metal Arm
 docs](arm-none-eabi.md#target-cpu-and-target-feature-options) for details on how
 to use these flags.
 
-### Table of supported CPUs
+### Table of supported CPUs for `thumbv8m.main-none-eabi`
 
 | CPU         | FPU | DSP | MVE       | Target CPU    | Target Features       |
 | ----------- | --- | --- | --------- | ------------- | --------------------- |
-| Cortex-M33  | No  | No  | N/A       | `cortex-m33`  | `+soft-float,-dsp`    |
-| Cortex-M33  | No  | Yes | N/A       | `cortex-m33`  | `+soft-float`         |
-| Cortex-M33  | SP  | No  | N/A       | `cortex-m33`  | `-dsp`                |
-| Cortex-M33  | SP  | Yes | N/A       | `cortex-m33`  | None                  |
-| Cortex-M35P | No  | No  | N/A       | `cortex-m35p` | `+soft-float,-dsp`    |
-| Cortex-M35P | No  | Yes | N/A       | `cortex-m35p` | `+soft-float`         |
-| Cortex-M35P | SP  | No  | N/A       | `cortex-m35p` | `-dsp`                |
-| Cortex-M35P | SP  | Yes | N/A       | `cortex-m35p` | None                  |
+| Unspecified | No  | No  | No        | None          | None                  |
+| Cortex-M33  | No  | No  | No        | `cortex-m33`  | `+soft-float,-dsp`    |
+| Cortex-M33  | No  | Yes | No        | `cortex-m33`  | `+soft-float`         |
+| Cortex-M33  | SP  | No  | No        | `cortex-m33`  | `-dsp`                |
+| Cortex-M33  | SP  | Yes | No        | `cortex-m33`  | None                  |
+| Cortex-M35P | No  | No  | No        | `cortex-m35p` | `+soft-float,-dsp`    |
+| Cortex-M35P | No  | Yes | No        | `cortex-m35p` | `+soft-float`         |
+| Cortex-M35P | SP  | No  | No        | `cortex-m35p` | `-dsp`                |
+| Cortex-M35P | SP  | Yes | No        | `cortex-m35p` | None                  |
 | Cortex-M55  | No  | Yes | No        | `cortex-m55`  | `+soft-float,-mve`    |
 | Cortex-M55  | DP  | Yes | No        | `cortex-m55`  | `-mve`                |
 | Cortex-M55  | No  | Yes | Int       | `cortex-m55`  | `+soft-float,-mve.fp` |
@@ -63,6 +58,22 @@ to use these flags.
 | Cortex-M85  | DP  | Yes | Int       | `cortex-m85`  | `-mve.fp`             |
 | Cortex-M85  | DP  | Yes | Int+Float | `cortex-m85`  | None                  |
 
+### Table of supported CPUs for `thumbv8m.main-none-eabihf`
+
+| CPU         | FPU | DSP | MVE       | Target CPU    | Target Features       |
+| ----------- | --- | --- | --------- | ------------- | --------------------- |
+| Unspecified | SP  | No  | No        | None          | None                  |
+| Cortex-M33  | SP  | No  | No        | `cortex-m33`  | `-dsp`                |
+| Cortex-M33  | SP  | Yes | No        | `cortex-m33`  | None                  |
+| Cortex-M33P | SP  | No  | No        | `cortex-m35p` | `-dsp`                |
+| Cortex-M33P | SP  | Yes | No        | `cortex-m35p` | None                  |
+| Cortex-M55  | DP  | Yes | No        | `cortex-m55`  | `-mve`                |
+| Cortex-M55  | DP  | Yes | Int       | `cortex-m55`  | `-mve.fp`             |
+| Cortex-M55  | DP  | Yes | Int+Float | `cortex-m55`  | None                  |
+| Cortex-M85  | DP  | Yes | No        | `cortex-m85`  | `-mve`                |
+| Cortex-M85  | DP  | Yes | Int       | `cortex-m85`  | `-mve.fp`             |
+| Cortex-M85  | DP  | Yes | Int+Float | `cortex-m85`  | None                  |
+
 ### Arm Cortex-M33
 
 The target CPU is `cortex-m33`.
@@ -72,7 +83,7 @@ The target CPU is `cortex-m33`.
   * enabled by default with this *target-cpu*
 * Has an optional single precision FPU
   * support is enabled by default with this *target-cpu*
-  * disable support using the `+soft-float` feature
+  * disable support using the `+soft-float` feature (`eabi` only)
 
 ### Arm Cortex-M35P
 
@@ -81,9 +92,9 @@ The target CPU is `cortex-m35p`.
 * Has optional DSP extensions
   * support is controlled by the `dsp` *target-feature*
   * enabled by default with this *target-cpu*
-* Has a single precision FPU
+* Has an optional single precision FPU
   * support is enabled by default with this *target-cpu*
-  * disable support using the `+soft-float` feature
+  * disable support using the `+soft-float` feature (`eabi` only)
 
 ### Arm Cortex-M55
 
@@ -95,7 +106,7 @@ The target CPU is `cortex-m55`.
 * Has an optional double-precision FPU that also supports half-precision FP16
   values
   * support is enabled by default with this *target-cpu*
-  * disable support using the `+soft-float` feature
+  * disable support using the `+soft-float` feature (`eabi` only)
 * Has optional support for M-Profile Vector Extensions
   * Also known as *Helium Technology*
   * Available with only integer support, or both integer/float support
@@ -114,7 +125,7 @@ The target CPU is `cortex-m85`.
 * Has an optional double-precision FPU that also supports half-precision FP16
   values
   * support is enabled by default with this *target-cpu*
-  * disable support using the `+soft-float` feature
+  * disable support using the `+soft-float` feature (`eabi` only)
 * Has optional support for M-Profile Vector Extensions
   * Also known as *Helium Technology*
   * Available with only integer support, or both integer/float support
diff --git a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabihf.md b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabihf.md
deleted file mode 100644
index 8f353a8d3db..00000000000
--- a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabihf.md
+++ /dev/null
@@ -1,113 +0,0 @@
-# `thumbv8m.main-none-eabihf`
-
-**Tier: 2**
-
-Bare-metal target for CPUs in the Mainline [ARMv8-M] architecture family,
-supporting a subset of the [T32 ISA][t32-isa].
-
-Processors in this family include the:
-
-* [Arm Cortex-M33F][cortex-m33]
-* [Arm Cortex-M55F][cortex-m55]
-* [Arm Cortex-M85F][cortex-m85]
-
-See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
-`arm-none-eabi` targets.
-
-This target uses the hard-float ABI: functions which take `f32` or `f64` as
-arguments will have them passed via FPU registers. This target therefore
-requires the use of an FPU (which is optional on Cortex-M33, Cortex-M55 and
-Cortex-M85). See also the soft-float ABI version of this target
-[`thumbv8m.main-none-eabi`](thumbv8m.main-none-eabi.md).
-
-[t32-isa]: https://developer.arm.com/Architectures/T32%20Instruction%20Set%20Architecture
-[ARMv8-M]: https://developer.arm.com/documentation/ddi0553/latest/
-[cortex-m33]: https://developer.arm.com/Processors/Cortex-M33
-[cortex-m55]: https://developer.arm.com/Processors/Cortex-M55
-[cortex-m85]: https://developer.arm.com/Processors/Cortex-M85
-
-## Target maintainers
-
-* [Rust Embedded Devices Working Group Cortex-M
-  Team](https://github.com/rust-embedded), `cortex-m@teams.rust-embedded.org`
-
-## Target CPU and Target Feature options
-
-See [the bare-metal Arm
-docs](arm-none-eabi.md#target-cpu-and-target-feature-options) for details on how
-to use these flags.
-
-### Table of supported CPUs
-
-| CPU         | FPU | DSP | MVE       | Target CPU    | Target Features       |
-| ----------- | --- | --- | --------- | ------------- | --------------------- |
-| Cortex-M33  | SP  | No  | N/A       | `cortex-m33`  | `-dsp`                |
-| Cortex-M33  | SP  | Yes | N/A       | `cortex-m33`  | None                  |
-| Cortex-M33P | SP  | No  | N/A       | `cortex-m35p` | `-dsp`                |
-| Cortex-M33P | SP  | Yes | N/A       | `cortex-m35p` | None                  |
-| Cortex-M55  | DP  | Yes | No        | `cortex-m55`  | `-mve`                |
-| Cortex-M55  | DP  | Yes | Int       | `cortex-m55`  | `-mve.fp`             |
-| Cortex-M55  | DP  | Yes | Int+Float | `cortex-m55`  | None                  |
-| Cortex-M85  | DP  | Yes | No        | `cortex-m85`  | `-mve`                |
-| Cortex-M85  | DP  | Yes | Int       | `cortex-m85`  | `-mve.fp`             |
-| Cortex-M85  | DP  | Yes | Int+Float | `cortex-m85`  | None                  |
-
-### Arm Cortex-M33
-
-The target CPU is `cortex-m33`.
-
-* Has optional DSP extensions
-  * support is controlled by the `dsp` *target-feature*
-  * enabled by default with this *target-cpu*
-* Has an optional single precision FPU
-  * support is enabled by default with this *target-cpu*
-  * support is required when using the hard-float ABI
-
-### Arm Cortex-M35P
-
-The target CPU is `cortex-m35p`.
-
-* Has optional DSP extensions
-  * support is controlled by the `dsp` *target-feature*
-  * enabled by default with this *target-cpu*
-* Has a single precision FPU
-  * support is enabled by default with this *target-cpu*
-  * support is required when using the hard-float ABI
-
-### Arm Cortex-M55
-
-The target CPU is `cortex-m55`.
-
-* Has DSP extensions
-  * support is controlled by the `dsp` *target-feature*
-  * enabled by default with this *target-cpu*
-* Has an optional double-precision FPU that also supports half-precision FP16
-  values
-  * support is enabled by default with this *target-cpu*
-  * support is required when using the hard-float ABI
-* Has optional support for M-Profile Vector Extensions
-  * Also known as *Helium Technology*
-  * Available with only integer support, or both integer/float support
-  * The appropriate feature for the MVE is either `mve` (integer) or `mve.fp`
-    (float)
-  * `mve.fp` is enabled by default on this target CPU
-  * disable using `-mve.fp` (disable float MVE) or `-mve` (disable all MVE)
-
-### Arm Cortex-M85
-
-The target CPU is `cortex-m85`.
-
-* Has DSP extensions
-  * support is controlled by the `dsp` *target-feature*
-  * enabled by default with this *target-cpu*
-* Has an optional double-precision FPU that also supports half-precision FP16
-  values
-  * support is enabled by default with this *target-cpu*
-  * support is required when using the hard-float ABI
-* Has optional support for M-Profile Vector Extensions
-  * Also known as *Helium Technology*
-  * Available with only integer support, or both integer/float support
-  * The appropriate feature for the MVE is either `mve` (integer) or `mve.fp`
-    (float)
-  * `mve.fp` is enabled by default on this target CPU
-  * disable using `-mve.fp` (disable float MVE) or `-mve` (disable all MVE)