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10 files changed, 185 insertions, 139 deletions

diff --git a/src/librustc_builtin_macros/asm.rs b/src/librustc_builtin_macros/asm.rs
index 943ed42e202..c9a3401cac0 100644
--- a/src/librustc_builtin_macros/asm.rs
+++ b/src/librustc_builtin_macros/asm.rs
@@ -80,47 +80,14 @@ fn parse_args<'a>(
             break;
         } // accept trailing commas
 
-        let span_start = p.token.span;
-
         // Parse options
         if p.eat(&token::Ident(sym::options, false)) {
-            p.expect(&token::OpenDelim(token::DelimToken::Paren))?;
-
-            while !p.eat(&token::CloseDelim(token::DelimToken::Paren)) {
-                if p.eat(&token::Ident(sym::pure, false)) {
-                    args.options |= InlineAsmOptions::PURE;
-                } else if p.eat(&token::Ident(sym::nomem, false)) {
-                    args.options |= InlineAsmOptions::NOMEM;
-                } else if p.eat(&token::Ident(sym::readonly, false)) {
-                    args.options |= InlineAsmOptions::READONLY;
-                } else if p.eat(&token::Ident(sym::preserves_flags, false)) {
-                    args.options |= InlineAsmOptions::PRESERVES_FLAGS;
-                } else if p.eat(&token::Ident(sym::noreturn, false)) {
-                    args.options |= InlineAsmOptions::NORETURN;
-                } else {
-                    p.expect(&token::Ident(sym::nostack, false))?;
-                    args.options |= InlineAsmOptions::NOSTACK;
-                }
-
-                // Allow trailing commas
-                if p.eat(&token::CloseDelim(token::DelimToken::Paren)) {
-                    break;
-                }
-                p.expect(&token::Comma)?;
-            }
-
-            let new_span = span_start.to(p.prev_token.span);
-            if let Some(options_span) = args.options_span {
-                ecx.struct_span_err(new_span, "asm options cannot be specified twice")
-                    .span_label(options_span, "previously here")
-                    .span_label(new_span, "duplicate options")
-                    .emit();
-            } else {
-                args.options_span = Some(new_span);
-            }
+            parse_options(&mut p, &mut args)?;
             continue;
         }
 
+        let span_start = p.token.span;
+
         // Parse operand names
         let name = if p.token.is_ident() && p.look_ahead(1, |t| *t == token::Eq) {
             let (ident, _) = p.token.ident().unwrap();
@@ -131,29 +98,6 @@ fn parse_args<'a>(
             None
         };
 
-        fn parse_reg<'a>(
-            p: &mut Parser<'a>,
-            explicit_reg: &mut bool,
-        ) -> Result<ast::InlineAsmRegOrRegClass, DiagnosticBuilder<'a>> {
-            p.expect(&token::OpenDelim(token::DelimToken::Paren))?;
-            let result = match p.token.kind {
-                token::Ident(name, false) => ast::InlineAsmRegOrRegClass::RegClass(name),
-                token::Literal(token::Lit { kind: token::LitKind::Str, symbol, suffix: _ }) => {
-                    *explicit_reg = true;
-                    ast::InlineAsmRegOrRegClass::Reg(symbol)
-                }
-                _ => {
-                    return Err(p.struct_span_err(
-                        p.token.span,
-                        "expected register class or explicit register",
-                    ));
-                }
-            };
-            p.bump();
-            p.expect(&token::CloseDelim(token::DelimToken::Paren))?;
-            Ok(result)
-        };
-
         let mut explicit_reg = false;
         let op = if p.eat(&token::Ident(kw::In, false)) {
             let reg = parse_reg(&mut p, &mut explicit_reg)?;
@@ -319,6 +263,69 @@ fn parse_args<'a>(
     Ok(args)
 }
 
+fn parse_options<'a>(p: &mut Parser<'a>, args: &mut AsmArgs) -> Result<(), DiagnosticBuilder<'a>> {
+    let span_start = p.prev_token.span;
+
+    p.expect(&token::OpenDelim(token::DelimToken::Paren))?;
+
+    while !p.eat(&token::CloseDelim(token::DelimToken::Paren)) {
+        if p.eat(&token::Ident(sym::pure, false)) {
+            args.options |= InlineAsmOptions::PURE;
+        } else if p.eat(&token::Ident(sym::nomem, false)) {
+            args.options |= InlineAsmOptions::NOMEM;
+        } else if p.eat(&token::Ident(sym::readonly, false)) {
+            args.options |= InlineAsmOptions::READONLY;
+        } else if p.eat(&token::Ident(sym::preserves_flags, false)) {
+            args.options |= InlineAsmOptions::PRESERVES_FLAGS;
+        } else if p.eat(&token::Ident(sym::noreturn, false)) {
+            args.options |= InlineAsmOptions::NORETURN;
+        } else {
+            p.expect(&token::Ident(sym::nostack, false))?;
+            args.options |= InlineAsmOptions::NOSTACK;
+        }
+
+        // Allow trailing commas
+        if p.eat(&token::CloseDelim(token::DelimToken::Paren)) {
+            break;
+        }
+        p.expect(&token::Comma)?;
+    }
+
+    let new_span = span_start.to(p.prev_token.span);
+    if let Some(options_span) = args.options_span {
+        p.struct_span_err(new_span, "asm options cannot be specified multiple times")
+            .span_label(options_span, "previously here")
+            .span_label(new_span, "duplicate options")
+            .emit();
+    } else {
+        args.options_span = Some(new_span);
+    }
+
+    Ok(())
+}
+
+fn parse_reg<'a>(
+    p: &mut Parser<'a>,
+    explicit_reg: &mut bool,
+) -> Result<ast::InlineAsmRegOrRegClass, DiagnosticBuilder<'a>> {
+    p.expect(&token::OpenDelim(token::DelimToken::Paren))?;
+    let result = match p.token.kind {
+        token::Ident(name, false) => ast::InlineAsmRegOrRegClass::RegClass(name),
+        token::Literal(token::Lit { kind: token::LitKind::Str, symbol, suffix: _ }) => {
+            *explicit_reg = true;
+            ast::InlineAsmRegOrRegClass::Reg(symbol)
+        }
+        _ => {
+            return Err(
+                p.struct_span_err(p.token.span, "expected register class or explicit register")
+            );
+        }
+    };
+    p.bump();
+    p.expect(&token::CloseDelim(token::DelimToken::Paren))?;
+    Ok(result)
+}
+
 fn expand_preparsed_asm(ecx: &mut ExtCtxt<'_>, sp: Span, args: AsmArgs) -> P<ast::Expr> {
     let msg = "asm template must be a string literal";
     let template_sp = args.template.span;
diff --git a/src/librustc_passes/intrinsicck.rs b/src/librustc_passes/intrinsicck.rs
index 1a9fd30bba0..b98ed99d04e 100644
--- a/src/librustc_passes/intrinsicck.rs
+++ b/src/librustc_passes/intrinsicck.rs
@@ -239,8 +239,10 @@ impl ExprVisitor<'tcx> {
                     &format!("type `{}`", self.tables.expr_ty_adjusted(in_expr)),
                 );
                 err.span_label(expr.span, &format!("type `{}`", ty));
-                err.note("asm inout arguments must have the same type");
-                err.note("unless they are both pointers or integers of the same size");
+                err.note(
+                    "asm inout arguments must have the same type, \
+                    unless they are both pointers or integers of the same size",
+                );
                 err.emit();
             }
 
@@ -271,7 +273,16 @@ impl ExprVisitor<'tcx> {
             }
         };
 
-        // Check whether the selected type requires a target feature.
+        // Check whether the selected type requires a target feature. Note that
+        // this is different from the feature check we did earlier in AST
+        // lowering. While AST lowering checked that this register class is
+        // usable at all with the currently enabled features, some types may
+        // only be usable with a register class when a certain feature is
+        // enabled. We check this here since it depends on the results of typeck.
+        //
+        // Also note that this check isn't run when the operand type is never
+        // (!). In that case we still need the earlier check in AST lowering to
+        // verify that the register class is usable at all.
         if let Some(feature) = feature {
             if !self.tcx.sess.target_features.contains(&Symbol::intern(feature)) {
                 let msg = &format!("`{}` target feature is not enabled", feature);
diff --git a/src/librustc_target/asm/aarch64.rs b/src/librustc_target/asm/aarch64.rs
index c734344f81f..16bc5d670d8 100644
--- a/src/librustc_target/asm/aarch64.rs
+++ b/src/librustc_target/asm/aarch64.rs
@@ -24,13 +24,10 @@ impl AArch64InlineAsmRegClass {
         ty: InlineAsmType,
     ) -> Option<(char, &'static str, Option<&'static str>)> {
         match self {
-            Self::reg => {
-                if ty.size().bits() <= 32 {
-                    Some(('w', "w0", None))
-                } else {
-                    None
-                }
-            }
+            Self::reg => match ty.size().bits() {
+                64 => None,
+                _ => Some(('w', "w0", None)),
+            },
             Self::vreg | Self::vreg_low16 => match ty.size().bits() {
                 8 => Some(('b', "b0", None)),
                 16 => Some(('h', "h0", None)),
@@ -57,8 +54,8 @@ impl AArch64InlineAsmRegClass {
             Self::reg => types! { _: I8, I16, I32, I64, F32, F64; },
             Self::vreg | Self::vreg_low16 => types! {
                 "fp": I8, I16, I32, I64, F32, F64,
-                VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2), VecF64(1),
-                VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2);
+                    VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2), VecF64(1),
+                    VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2);
             },
         }
     }
@@ -128,12 +125,12 @@ def_regs! {
         v29: vreg = ["v29", "b29", "h29", "s29", "d29", "q29"],
         v30: vreg = ["v30", "b30", "h30", "s30", "d30", "q30"],
         v31: vreg = ["v31", "b31", "h31", "s31", "d31", "q31"],
-        "the frame pointer cannot be used as an operand for inline asm" =
-            ["x29", "fp"],
-        "the stack pointer cannot be used as an operand for inline asm" =
-            ["sp", "wsp"],
-        "the zero register cannot be used as an operand for inline asm" =
-            ["xzr", "wzr"],
+        #error = ["x29", "fp"] =>
+            "the frame pointer cannot be used as an operand for inline asm",
+        #error = ["sp", "wsp"] =>
+            "the stack pointer cannot be used as an operand for inline asm",
+        #error = ["xzr", "wzr"] =>
+            "the zero register cannot be used as an operand for inline asm",
     }
 }
 
diff --git a/src/librustc_target/asm/arm.rs b/src/librustc_target/asm/arm.rs
index 143852db829..0ceb15e297f 100644
--- a/src/librustc_target/asm/arm.rs
+++ b/src/librustc_target/asm/arm.rs
@@ -149,12 +149,12 @@ def_regs! {
         q13: qreg = ["q13"],
         q14: qreg = ["q14"],
         q15: qreg = ["q15"],
-        "the frame pointer cannot be used as an operand for inline asm" =
-            ["r11", "fp"],
-        "the stack pointer cannot be used as an operand for inline asm" =
-            ["r13", "sp"],
-        "the program pointer cannot be used as an operand for inline asm" =
-            ["r15", "pc"],
+        #error = ["r11", "fp"] =>
+            "the frame pointer cannot be used as an operand for inline asm",
+        #error = ["r13", "sp"] =>
+            "the stack pointer cannot be used as an operand for inline asm",
+        #error = ["r15", "pc"] =>
+            "the program pointer cannot be used as an operand for inline asm",
     }
 }
 
@@ -231,6 +231,15 @@ impl ArmInlineAsmReg {
                 }
             };
         }
+
+        // ARM's floating-point register file is interesting in that it can be
+        // viewed as 16 128-bit registers, 32 64-bit registers or 32 32-bit
+        // registers. Because these views overlap, the registers of different
+        // widths will conflict (e.g. d0 overlaps with s0 and s1, and q1
+        // overlaps with d2 and d3).
+        //
+        // See section E1.3.1 of the ARM Architecture Reference Manual for
+        // ARMv8-A for more details.
         reg_conflicts! {
             q0 : d0 d1 : s0 s1 s2 s3,
             q1 : d2 d3 : s4 s5 s6 s7,
diff --git a/src/librustc_target/asm/mod.rs b/src/librustc_target/asm/mod.rs
index 1f8ff5d6d39..dda6e7cd5cd 100644
--- a/src/librustc_target/asm/mod.rs
+++ b/src/librustc_target/asm/mod.rs
@@ -57,7 +57,7 @@ macro_rules! def_regs {
             $reg:ident: $class:ident $(, $extra_class:ident)* = [$reg_name:literal $(, $alias:literal)*] $(% $filter:ident)?,
         )*
         $(
-            $error:literal = [$($bad_reg:literal),+],
+            #error = [$($bad_reg:literal),+] => $error:literal,
         )*
     }) => {
         #[derive(Copy, Clone, RustcEncodable, RustcDecodable, Debug, Eq, PartialEq, Hash, HashStable_Generic)]
diff --git a/src/librustc_target/asm/riscv.rs b/src/librustc_target/asm/riscv.rs
index c57e277c0cd..f9b132c2087 100644
--- a/src/librustc_target/asm/riscv.rs
+++ b/src/librustc_target/asm/riscv.rs
@@ -115,16 +115,16 @@ def_regs! {
         f29: freg = ["f29", "ft9"],
         f30: freg = ["f30", "ft10"],
         f31: freg = ["f31", "ft11"],
-        "the frame pointer cannot be used as an operand for inline asm" =
-            ["x8", "s0", "fp"],
-        "the stack pointer cannot be used as an operand for inline asm" =
-            ["x2", "sp"],
-        "the global pointer cannot be used as an operand for inline asm" =
-            ["x3", "gp"],
-        "the thread pointer cannot be used as an operand for inline asm" =
-            ["x4", "tp"],
-        "the zero register cannot be used as an operand for inline asm" =
-            ["x0", "zero"],
+        #error = ["x8", "s0", "fp"] =>
+            "the frame pointer cannot be used as an operand for inline asm",
+        #error = ["x2", "sp"] =>
+            "the stack pointer cannot be used as an operand for inline asm",
+        #error = ["x3", "gp"] =>
+            "the global pointer cannot be used as an operand for inline asm",
+        #error = ["x4", "tp"] =>
+            "the thread pointer cannot be used as an operand for inline asm" ,
+        #error = ["x0", "zero"] =>
+            "the zero register cannot be used as an operand for inline asm",
     }
 }
 
diff --git a/src/librustc_target/asm/x86.rs b/src/librustc_target/asm/x86.rs
index 7193b1ca8b6..d10bcb40ba0 100644
--- a/src/librustc_target/asm/x86.rs
+++ b/src/librustc_target/asm/x86.rs
@@ -62,16 +62,13 @@ impl X86InlineAsmRegClass {
                 _ => None,
             },
             Self::xmm_reg => None,
-            Self::ymm_reg => {
-                if ty.size().bits() <= 128 {
-                    Some(('x', "xmm0", None))
-                } else {
-                    None
-                }
-            }
+            Self::ymm_reg => match ty.size().bits() {
+                256 => None,
+                _ => Some(('x', "xmm0", None)),
+            },
             Self::zmm_reg => match ty.size().bits() {
-                256 => Some(('y', "ymm0", None)),
                 512 => None,
+                256 => Some(('y', "ymm0", None)),
                 _ => Some(('x', "xmm0", None)),
             },
             Self::kreg => None,
@@ -108,18 +105,18 @@ impl X86InlineAsmRegClass {
             }
             Self::xmm_reg => types! {
                 "sse": I32, I64, F32, F64,
-                VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2);
+                  VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2);
             },
             Self::ymm_reg => types! {
                 "avx": I32, I64, F32, F64,
-                VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2),
-                VecI8(32), VecI16(16), VecI32(8), VecI64(4), VecF32(8), VecF64(4);
+                    VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2),
+                    VecI8(32), VecI16(16), VecI32(8), VecI64(4), VecF32(8), VecF64(4);
             },
             Self::zmm_reg => types! {
                 "avx512f": I32, I64, F32, F64,
-                VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2),
-                VecI8(32), VecI16(16), VecI32(8), VecI64(4), VecF32(8), VecF64(4),
-                VecI8(64), VecI16(32), VecI32(16), VecI64(8), VecF32(16), VecF64(8);
+                    VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2),
+                    VecI8(32), VecI16(16), VecI32(8), VecI64(4), VecF32(8), VecF64(4),
+                    VecI8(64), VecI16(32), VecI32(16), VecI64(8), VecF32(16), VecF64(8);
             },
             Self::kreg => types! {
                 "avx512f": I8, I16;
@@ -227,19 +224,20 @@ def_regs! {
         k5: kreg = ["k5"],
         k6: kreg = ["k6"],
         k7: kreg = ["k7"],
-        "high byte registers are not currently supported as operands for inline asm" =
-            ["ah", "bh", "ch", "dh"],
-        "the frame pointer cannot be used as an operand for inline asm" =
-            ["bp", "bpl", "ebp", "rbp"],
-        "the stack pointer cannot be used as an operand for inline asm" =
-            ["sp", "spl", "esp", "rsp"],
-        "the instruction pointer cannot be used as an operand for inline asm" =
-            ["ip", "eip", "rip"],
-        "x87 registers are not currently supported as operands for inline asm" =
-            ["st", "st(0)", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)"],
-        "MMX registers are not currently supported as operands for inline asm" =
-            ["mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"],
-        "the k0 AVX mask register cannot be used as an operand for inline asm" = ["k0"],
+        #error = ["ah", "bh", "ch", "dh"] =>
+            "high byte registers are not currently supported as operands for inline asm",
+        #error = ["bp", "bpl", "ebp", "rbp"] =>
+            "the frame pointer cannot be used as an operand for inline asm",
+        #error = ["sp", "spl", "esp", "rsp"] =>
+            "the stack pointer cannot be used as an operand for inline asm",
+        #error = ["ip", "eip", "rip"] =>
+            "the instruction pointer cannot be used as an operand for inline asm",
+        #error = ["st", "st(0)", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)"] =>
+            "x87 registers are not currently supported as operands for inline asm",
+        #error = ["mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"] =>
+            "MMX registers are not currently supported as operands for inline asm",
+        #error = ["k0"] =>
+            "the k0 AVX mask register cannot be used as an operand for inline asm",
     }
 }
 
@@ -316,6 +314,15 @@ impl X86InlineAsmReg {
                 }
             };
         }
+
+        // XMM*, YMM* and ZMM* are all different views of the same register.
+        //
+        // See section 15.5 of the combined Intel® 64 and IA-32 Architectures
+        // Software Developer’s Manual for more details.
+        //
+        // We don't need to specify conflicts for [x,y,z]mm[16-31] since these
+        // registers are only available with AVX-512, so we just specify them
+        // as aliases directly.
         reg_conflicts! {
             xmm0 : ymm0 : zmm0,
             xmm1 : ymm1 : zmm1,
diff --git a/src/test/ui/asm/parse-error.rs b/src/test/ui/asm/parse-error.rs
index e6566866b22..2b1f018f364 100644
--- a/src/test/ui/asm/parse-error.rs
+++ b/src/test/ui/asm/parse-error.rs
@@ -35,7 +35,10 @@ fn main() {
         asm!("", options(nomem, foo));
         //~^ ERROR expected one of
         asm!("", options(), options());
-        //~^ ERROR asm options cannot be specified twice
+        //~^ ERROR asm options cannot be specified multiple times
+        asm!("", options(), options(), options());
+        //~^ ERROR asm options cannot be specified multiple times
+        //~^^ ERROR asm options cannot be specified multiple times
         asm!("{}", options(), const foo);
         //~^ ERROR arguments are not allowed after options
         asm!("{a}", a = const foo, a = const bar);
diff --git a/src/test/ui/asm/parse-error.stderr b/src/test/ui/asm/parse-error.stderr
index a927ce13858..94eb9d29862 100644
--- a/src/test/ui/asm/parse-error.stderr
+++ b/src/test/ui/asm/parse-error.stderr
@@ -82,7 +82,7 @@ error: expected one of `)`, `nomem`, `noreturn`, `nostack`, `preserves_flags`, `
 LL |         asm!("", options(nomem, foo));
    |                                 ^^^ expected one of 7 possible tokens
 
-error: asm options cannot be specified twice
+error: asm options cannot be specified multiple times
   --> $DIR/parse-error.rs:37:29
    |
 LL |         asm!("", options(), options());
@@ -90,8 +90,24 @@ LL |         asm!("", options(), options());
    |                  |
    |                  previously here
 
+error: asm options cannot be specified multiple times
+  --> $DIR/parse-error.rs:39:29
+   |
+LL |         asm!("", options(), options(), options());
+   |                  ---------  ^^^^^^^^^ duplicate options
+   |                  |
+   |                  previously here
+
+error: asm options cannot be specified multiple times
+  --> $DIR/parse-error.rs:39:40
+   |
+LL |         asm!("", options(), options(), options());
+   |                  ---------             ^^^^^^^^^ duplicate options
+   |                  |
+   |                  previously here
+
 error: arguments are not allowed after options
-  --> $DIR/parse-error.rs:39:31
+  --> $DIR/parse-error.rs:42:31
    |
 LL |         asm!("{}", options(), const foo);
    |                    ---------  ^^^^^^^^^ argument
@@ -99,7 +115,7 @@ LL |         asm!("{}", options(), const foo);
    |                    previous options
 
 error: duplicate argument named `a`
-  --> $DIR/parse-error.rs:41:36
+  --> $DIR/parse-error.rs:44:36
    |
 LL |         asm!("{a}", a = const foo, a = const bar);
    |                     -------------  ^^^^^^^^^^^^^ duplicate argument
@@ -107,19 +123,19 @@ LL |         asm!("{a}", a = const foo, a = const bar);
    |                     previously here
 
 error: argument never used
-  --> $DIR/parse-error.rs:41:36
+  --> $DIR/parse-error.rs:44:36
    |
 LL |         asm!("{a}", a = const foo, a = const bar);
    |                                    ^^^^^^^^^^^^^ argument never used
 
 error: explicit register arguments cannot have names
-  --> $DIR/parse-error.rs:44:18
+  --> $DIR/parse-error.rs:47:18
    |
 LL |         asm!("", a = in("eax") foo);
    |                  ^^^^^^^^^^^^^^^^^
 
 error: named arguments cannot follow explicit register arguments
-  --> $DIR/parse-error.rs:46:36
+  --> $DIR/parse-error.rs:49:36
    |
 LL |         asm!("{a}", in("eax") foo, a = const bar);
    |                     -------------  ^^^^^^^^^^^^^ named argument
@@ -127,7 +143,7 @@ LL |         asm!("{a}", in("eax") foo, a = const bar);
    |                     explicit register argument
 
 error: named arguments cannot follow explicit register arguments
-  --> $DIR/parse-error.rs:48:36
+  --> $DIR/parse-error.rs:51:36
    |
 LL |         asm!("{a}", in("eax") foo, a = const bar);
    |                     -------------  ^^^^^^^^^^^^^ named argument
@@ -135,12 +151,12 @@ LL |         asm!("{a}", in("eax") foo, a = const bar);
    |                     explicit register argument
 
 error: positional arguments cannot follow named arguments or explicit register arguments
-  --> $DIR/parse-error.rs:50:36
+  --> $DIR/parse-error.rs:53:36
    |
 LL |         asm!("{1}", in("eax") foo, const bar);
    |                     -------------  ^^^^^^^^^ positional argument
    |                     |
    |                     explicit register argument
 
-error: aborting due to 22 previous errors
+error: aborting due to 24 previous errors
 
diff --git a/src/test/ui/asm/type-check-3.stderr b/src/test/ui/asm/type-check-3.stderr
index e4018ca1d42..ccc795d1013 100644
--- a/src/test/ui/asm/type-check-3.stderr
+++ b/src/test/ui/asm/type-check-3.stderr
@@ -83,8 +83,7 @@ LL |         asm!("{:r}", inout(reg) 0u16 => val_i8);
    |                                 |
    |                                 type `u16`
    |
-   = note: asm inout arguments must have the same type
-   = note: unless they are both pointers or integers of the same size
+   = note: asm inout arguments must have the same type, unless they are both pointers or integers of the same size
 
 error: incompatible types for asm inout argument
   --> $DIR/type-check-3.rs:59:33
@@ -94,8 +93,7 @@ LL |         asm!("{:r}", inout(reg) 0u32 => val_f32);
    |                                 |
    |                                 type `u32`
    |
-   = note: asm inout arguments must have the same type
-   = note: unless they are both pointers or integers of the same size
+   = note: asm inout arguments must have the same type, unless they are both pointers or integers of the same size
 
 error: incompatible types for asm inout argument
   --> $DIR/type-check-3.rs:61:33
@@ -105,8 +103,7 @@ LL |         asm!("{:r}", inout(reg) 0u32 => val_ptr);
    |                                 |
    |                                 type `u32`
    |
-   = note: asm inout arguments must have the same type
-   = note: unless they are both pointers or integers of the same size
+   = note: asm inout arguments must have the same type, unless they are both pointers or integers of the same size
 
 error: incompatible types for asm inout argument
   --> $DIR/type-check-3.rs:63:33
@@ -116,8 +113,7 @@ LL |         asm!("{:r}", inout(reg) main => val_u32);
    |                                 |
    |                                 type `fn()`
    |
-   = note: asm inout arguments must have the same type
-   = note: unless they are both pointers or integers of the same size
+   = note: asm inout arguments must have the same type, unless they are both pointers or integers of the same size
 
 error: aborting due to 9 previous errors; 4 warnings emitted