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| author | bors <bors@rust-lang.org> | 2023-06-02 23:02:42 +0000 |
|---|---|---|
| committer | bors <bors@rust-lang.org> | 2023-06-02 23:02:42 +0000 |
| commit | 7a0070eaeadf6cd4641197401f0554bad12532eb (patch) | |
| tree | 9e318c68a45ffbb209396b34288b23bfb9cceddb /compiler/rustc_codegen_cranelift/src | |
| parent | dd5d7c729d4e8a59708df64002e09dbcbc4005ba (diff) | |
| parent | 18763cb464e911a840ee5bd45093cd3fbadaf52d (diff) | |
| download | rust-7a0070eaeadf6cd4641197401f0554bad12532eb.tar.gz rust-7a0070eaeadf6cd4641197401f0554bad12532eb.zip | |
Auto merge of #112228 - compiler-errors:rollup-97i0pli, r=compiler-errors
Rollup of 6 pull requests Successful merges: - #109609 (Separate AnonConst from ConstBlock in HIR.) - #112166 (bootstrap: Rename profile = user to profile = dist) - #112168 (Lower `unchecked_div`/`_rem` to MIR's `BinOp::Div`/`Rem`) - #112183 (Normalize anon consts in new solver) - #112211 (pass `--lib` to `x doc`) - #112223 (Don't ICE in new solver when auto traits have associated types) r? `@ghost` `@rustbot` modify labels: rollup
Diffstat (limited to 'compiler/rustc_codegen_cranelift/src')
| -rw-r--r-- | compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs b/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs index 0a513b08b74..1e83c30bd67 100644 --- a/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs +++ b/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs @@ -475,9 +475,7 @@ fn codegen_regular_intrinsic_call<'tcx>( sym::unchecked_add | sym::unchecked_sub | sym::unchecked_mul - | sym::unchecked_div | sym::exact_div - | sym::unchecked_rem | sym::unchecked_shl | sym::unchecked_shr => { intrinsic_args!(fx, args => (x, y); intrinsic); @@ -487,8 +485,7 @@ fn codegen_regular_intrinsic_call<'tcx>( sym::unchecked_add => BinOp::Add, sym::unchecked_sub => BinOp::Sub, sym::unchecked_mul => BinOp::Mul, - sym::unchecked_div | sym::exact_div => BinOp::Div, - sym::unchecked_rem => BinOp::Rem, + sym::exact_div => BinOp::Div, sym::unchecked_shl => BinOp::Shl, sym::unchecked_shr => BinOp::Shr, _ => unreachable!(), |