diff options
| author | Amanieu d'Antras <amanieu@gmail.com> | 2022-07-11 14:26:58 +0100 |
|---|---|---|
| committer | Amanieu d'Antras <amanieu@gmail.com> | 2022-07-11 14:26:58 +0100 |
| commit | e51f1b7e275584872525bbfbd7c481595b99f237 (patch) | |
| tree | ef52561e7cbc5a173e79f07186424b8241f6c0b6 /compiler/rustc_codegen_gcc | |
| parent | 50b00252aeb77b10db04d65dc9e12ce758def4b5 (diff) | |
| download | rust-e51f1b7e275584872525bbfbd7c481595b99f237.tar.gz rust-e51f1b7e275584872525bbfbd7c481595b99f237.zip | |
Keep unstable target features for asm feature checking
Inline assembly uses the target features to determine which registers are available on the current target. However it needs to be able to access unstable target features for this. Fixes #99071
Diffstat (limited to 'compiler/rustc_codegen_gcc')
| -rw-r--r-- | compiler/rustc_codegen_gcc/src/lib.rs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/compiler/rustc_codegen_gcc/src/lib.rs b/compiler/rustc_codegen_gcc/src/lib.rs index 58996a9db78..91c1fa6026c 100644 --- a/compiler/rustc_codegen_gcc/src/lib.rs +++ b/compiler/rustc_codegen_gcc/src/lib.rs @@ -133,8 +133,8 @@ impl CodegenBackend for GccCodegenBackend { ) } - fn target_features(&self, sess: &Session) -> Vec<Symbol> { - target_features(sess) + fn target_features(&self, sess: &Session, allow_unstable: bool) -> Vec<Symbol> { + target_features(sess, allow_unstable) } } @@ -291,12 +291,12 @@ pub fn target_cpu(sess: &Session) -> &str { } } -pub fn target_features(sess: &Session) -> Vec<Symbol> { +pub fn target_features(sess: &Session, allow_unstable: bool) -> Vec<Symbol> { supported_target_features(sess) .iter() .filter_map( |&(feature, gate)| { - if sess.is_nightly_build() || gate.is_none() { Some(feature) } else { None } + if sess.is_nightly_build() || allow_unstable || gate.is_none() { Some(feature) } else { None } }, ) .filter(|_feature| { |
