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| author | bors <bors@rust-lang.org> | 2022-04-03 21:22:50 +0000 |
|---|---|---|
| committer | bors <bors@rust-lang.org> | 2022-04-03 21:22:50 +0000 |
| commit | 6af09d2505f38e4f1df291df56d497fb2ad935ed (patch) | |
| tree | b0006d75855880faca5257f11ff60d90505b9e93 /compiler/rustc_codegen_llvm/src/context.rs | |
| parent | 2ad4eb207b369017f5140918b5e4b0d3650b46b0 (diff) | |
| parent | 1ea6e936106cbf93d8b32844f2d2598a599a89b4 (diff) | |
| download | rust-6af09d2505f38e4f1df291df56d497fb2ad935ed.tar.gz rust-6af09d2505f38e4f1df291df56d497fb2ad935ed.zip | |
Auto merge of #95624 - Dylan-DPC:rollup-r8w7ui3, r=Dylan-DPC
Rollup of 5 pull requests Successful merges: - #95202 (Reduce the cost of loading all built-ins targets) - #95553 (Don't emit non-asm contents error for naked function composed of errors) - #95613 (Fix rustdoc attribute display) - #95617 (Fix &mut invalidation in ptr::swap doctest) - #95618 (core: document that the align_of* functions return the alignment in bytes) Failed merges: r? `@ghost` `@rustbot` modify labels: rollup
Diffstat (limited to 'compiler/rustc_codegen_llvm/src/context.rs')
| -rw-r--r-- | compiler/rustc_codegen_llvm/src/context.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler/rustc_codegen_llvm/src/context.rs b/compiler/rustc_codegen_llvm/src/context.rs index 712431ca9ae..98cf873ebbd 100644 --- a/compiler/rustc_codegen_llvm/src/context.rs +++ b/compiler/rustc_codegen_llvm/src/context.rs @@ -134,7 +134,7 @@ pub unsafe fn create_module<'ll>( let mod_name = SmallCStr::new(mod_name); let llmod = llvm::LLVMModuleCreateWithNameInContext(mod_name.as_ptr(), llcx); - let mut target_data_layout = sess.target.data_layout.clone(); + let mut target_data_layout = sess.target.data_layout.to_string(); let llvm_version = llvm_util::get_version(); if llvm_version < (13, 0, 0) { if sess.target.arch == "powerpc64" { @@ -859,7 +859,7 @@ impl<'ll> CodegenCx<'ll, '_> { // This isn't an "LLVM intrinsic", but LLVM's optimization passes // recognize it like one and we assume it exists in `core::slice::cmp` - match self.sess().target.arch.as_str() { + match self.sess().target.arch.as_ref() { "avr" | "msp430" => ifn!("memcmp", fn(i8p, i8p, t_isize) -> t_i16), _ => ifn!("memcmp", fn(i8p, i8p, t_isize) -> t_i32), } |