rustc_target: RISC-V: add base "I"-related important extensions

Of ratified RISC-V features defined, this commit adds extensions
satisfying following criteria:

*   Formerly a part of the "I" extension and splitted thereafter
    (now ratified as "I" + "Zifencei" + "Zicsr" + "Zicntr" + "Zihpm") or
*   Dicoverable from newer versions of the Linux kernel and implemented
    as a part of std_detect's feature ("Zihintpause").

This is based on the latest ratified ISA Manuals (version 20240411).

Additional (1):

One of those, "Zicsr", is a dependency of many other ISA extensions and
this commit adds correct dependencies to "Zicsr".

Additional (2):

In RISC-V, "G" is an abbreviation of following extensions:

*   "I"
*   "M"
*   "A"
*   "F"
*   "D"
*   "Zicsr" (although implied by "F")
*   "Zifencei"

and all RISC-V targets with the "G" abbreviation and targets for Android /
VxWorks are updated accordingly.

Note:

Android will require RVA22 (likely RVA22U64) and some more extensions,
which is a superset of RV64GC.  For VxWorks, all BSPs currently distributed
by Wind River are for boards with RV64GC (this commit also updates
riscv32-wrs-vxworks though).

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