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| author | Amanieu d'Antras <amanieu@gmail.com> | 2022-07-11 14:26:58 +0100 |
|---|---|---|
| committer | Amanieu d'Antras <amanieu@gmail.com> | 2022-07-11 14:26:58 +0100 |
| commit | e51f1b7e275584872525bbfbd7c481595b99f237 (patch) | |
| tree | ef52561e7cbc5a173e79f07186424b8241f6c0b6 /compiler/rustc_codegen_llvm/src/lib.rs | |
| parent | 50b00252aeb77b10db04d65dc9e12ce758def4b5 (diff) | |
| download | rust-e51f1b7e275584872525bbfbd7c481595b99f237.tar.gz rust-e51f1b7e275584872525bbfbd7c481595b99f237.zip | |
Keep unstable target features for asm feature checking
Inline assembly uses the target features to determine which registers are available on the current target. However it needs to be able to access unstable target features for this. Fixes #99071
Diffstat (limited to 'compiler/rustc_codegen_llvm/src/lib.rs')
| -rw-r--r-- | compiler/rustc_codegen_llvm/src/lib.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler/rustc_codegen_llvm/src/lib.rs b/compiler/rustc_codegen_llvm/src/lib.rs index 913cf4eea13..c87d9a5406d 100644 --- a/compiler/rustc_codegen_llvm/src/lib.rs +++ b/compiler/rustc_codegen_llvm/src/lib.rs @@ -324,8 +324,8 @@ impl CodegenBackend for LlvmCodegenBackend { llvm_util::print_version(); } - fn target_features(&self, sess: &Session) -> Vec<Symbol> { - target_features(sess) + fn target_features(&self, sess: &Session, allow_unstable: bool) -> Vec<Symbol> { + target_features(sess, allow_unstable) } fn codegen_crate<'tcx>( |