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| author | Stuart Cook <Zalathar@users.noreply.github.com> | 2025-08-04 11:24:37 +1000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-04 11:24:37 +1000 |
| commit | 70587ebf0d3a6060e08bfb9c2d07dfdbfd8b2918 (patch) | |
| tree | 772c9d0300613bd4aadf082b984f57fdd6e4913b /compiler/rustc_codegen_llvm/src | |
| parent | cc7c63b907c951fccc29bdc913edc7006aa58a9b (diff) | |
| parent | 6c7dc05f7d1f000cdb7de2390c8532545129e32d (diff) | |
| download | rust-70587ebf0d3a6060e08bfb9c2d07dfdbfd8b2918.tar.gz rust-70587ebf0d3a6060e08bfb9c2d07dfdbfd8b2918.zip | |
Rollup merge of #144559 - CaiWeiran:extract-insert-dyn_test, r=Mark-Simulacrum
Enable extract-insert-dyn.rs test on RISC-V (riscv64) This PR adds support for running the `tests/codegen-llvm/simd/extract-insert-dyn.rs` test on the RISC-V (riscv64) architecture. Previously, this test would fail on RISC-V targets due to architecture-specific code generation issues. This patch modifies the test to ensure compatibility while preserving its intent. The change has been tested locally using `./x test` on a riscv64 target, and the test now passes as expected. ### Notes: - This change is scoped specifically to improve RISC-V compatibility. - It does not affect behavior or test results on other architectures.
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