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authorJubilee <46493976+workingjubilee@users.noreply.github.com>2024-03-12 09:03:59 -0700
committerGitHub <noreply@github.com>2024-03-12 09:03:59 -0700
commit947d9602437562ebf0c981fdaadb9ec4e76de469 (patch)
tree130de3904eec07ffde0175b5035290b9808697a1 /compiler/rustc_codegen_llvm/src
parent7a45c72f24b42170192edfa17078a82970f8fcf5 (diff)
parente91f93777997ee647768afa60d565a0a62aefa49 (diff)
downloadrust-947d9602437562ebf0c981fdaadb9ec4e76de469.tar.gz
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Rollup merge of #121953 - jhorstmann:assembly-tests-for-masked-simd-instructions, r=workingjubilee
Add tests for the generated assembly of mask related simd instructions.

The tests show that the code generation currently uses the least significant bits of <iX x N> vector masks when converting to <i1 xN>. This leads to an additional left shift operation in the assembly for x86, since mask operations on x86 operate based on the most significant bit.

The exception is simd_bitmask, which already uses the most-significant bit.

This additional instruction would be removed by the changes in #104693, which makes all mask operations consistently use the most significant bits.

By using the "C" calling convention the tests should be stable regarding changes in register allocation, but it is possible that future llvm updates will require updating some of the checks.
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