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authorbors <bors@rust-lang.org>2024-03-18 16:51:07 +0000
committerbors <bors@rust-lang.org>2024-03-18 16:51:07 +0000
commitd31b6fb8c06b43536ac5be38462d2a55784e2199 (patch)
tree7919dd4a877756bd4660fad0aadc9c6e015d71af /compiler/rustc_codegen_llvm/src
parent3cdcdaf31b45f8045164aae9604573d23091970b (diff)
parent9011e67c91938ce9c7e9e55d233e5540abd333a3 (diff)
downloadrust-d31b6fb8c06b43536ac5be38462d2a55784e2199.tar.gz
rust-d31b6fb8c06b43536ac5be38462d2a55784e2199.zip
Auto merge of #122690 - matthiaskrgr:rollup-43fggl0, r=matthiaskrgr
Rollup of 8 pull requests

Successful merges:

 - #122480 (Avoid various uses of `Option<Span>` in favor of using `DUMMY_SP` in the few cases that used `None`)
 - #122567 (Remove fixme about LLVM basic block naming)
 - #122588 (less useless filter calls in imported_source_file)
 - #122647 (add_retag: ensure box-to-raw-ptr casts are preserved for Miri)
 - #122649 (Update the minimum external LLVM to 17)
 - #122680 (Do not eat nested expressions' results in `MayContainYieldPoint` format args visitor)
 - #122683 (add missing test: expected paren or brace in macro)
 - #122689 (Add missing `try_visit` calls in visitors.)

r? `@ghost`
`@rustbot` modify labels: rollup
Diffstat (limited to 'compiler/rustc_codegen_llvm/src')
-rw-r--r--compiler/rustc_codegen_llvm/src/context.rs11
-rw-r--r--compiler/rustc_codegen_llvm/src/intrinsic.rs2
2 files changed, 1 insertions, 12 deletions
diff --git a/compiler/rustc_codegen_llvm/src/context.rs b/compiler/rustc_codegen_llvm/src/context.rs
index f89c8c9f836..c3f17563b0a 100644
--- a/compiler/rustc_codegen_llvm/src/context.rs
+++ b/compiler/rustc_codegen_llvm/src/context.rs
@@ -126,17 +126,6 @@ pub unsafe fn create_module<'ll>(
 
     let mut target_data_layout = sess.target.data_layout.to_string();
     let llvm_version = llvm_util::get_version();
-    if llvm_version < (17, 0, 0) {
-        if sess.target.arch.starts_with("powerpc") {
-            // LLVM 17 specifies function pointer alignment for ppc:
-            // https://reviews.llvm.org/D147016
-            target_data_layout = target_data_layout
-                .replace("-Fn32", "")
-                .replace("-Fi32", "")
-                .replace("-Fn64", "")
-                .replace("-Fi64", "");
-        }
-    }
     if llvm_version < (18, 0, 0) {
         if sess.target.arch == "x86" || sess.target.arch == "x86_64" {
             // LLVM 18 adjusts i128 to be 128-bit aligned on x86 variants.
diff --git a/compiler/rustc_codegen_llvm/src/intrinsic.rs b/compiler/rustc_codegen_llvm/src/intrinsic.rs
index 467e02d55e3..71b69a94e99 100644
--- a/compiler/rustc_codegen_llvm/src/intrinsic.rs
+++ b/compiler/rustc_codegen_llvm/src/intrinsic.rs
@@ -1129,7 +1129,7 @@ fn generic_simd_intrinsic<'ll, 'tcx>(
     if name == sym::simd_shuffle_generic {
         let idx = fn_args[2]
             .expect_const()
-            .eval(tcx, ty::ParamEnv::reveal_all(), Some(span))
+            .eval(tcx, ty::ParamEnv::reveal_all(), span)
             .unwrap()
             .unwrap_branch();
         let n = idx.len() as u64;