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| author | Tim Neumann <timnn@google.com> | 2022-11-06 19:03:22 +0000 |
|---|---|---|
| committer | Tim Neumann <timnn@google.com> | 2022-11-06 19:03:22 +0000 |
| commit | f414715ebfda201f91f80ef9f28d9923d614d1c4 (patch) | |
| tree | 5734a93eb1e57c06bb1d355bd620b263d486ee42 /compiler/rustc_codegen_llvm/src | |
| parent | 1e1e5b8d98750a162335f64ec3c792ce80c9866c (diff) | |
| download | rust-f414715ebfda201f91f80ef9f28d9923d614d1c4.tar.gz rust-f414715ebfda201f91f80ef9f28d9923d614d1c4.zip | |
LLVM 16: Update RISCV data layout
Diffstat (limited to 'compiler/rustc_codegen_llvm/src')
| -rw-r--r-- | compiler/rustc_codegen_llvm/src/context.rs | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/compiler/rustc_codegen_llvm/src/context.rs b/compiler/rustc_codegen_llvm/src/context.rs index 79ddfd884df..c22ec128dac 100644 --- a/compiler/rustc_codegen_llvm/src/context.rs +++ b/compiler/rustc_codegen_llvm/src/context.rs @@ -158,6 +158,10 @@ pub unsafe fn create_module<'ll>( if sess.target.arch == "s390x" { target_data_layout = target_data_layout.replace("-v128:64", ""); } + + if sess.target.arch == "riscv64" { + target_data_layout = target_data_layout.replace("-n32:64-", "-n64-"); + } } // Ensure the data-layout values hardcoded remain the defaults. |