Auto merge of #115787 - Mark-Simulacrum:stable-next, r=Mark-Simulacrum 1.72.1

[stable] 1.72.1 release

This backports:

*  Remove assert that checks type equality #115215
*  implied bounds: do not ICE on unconstrained region vars #115559
*  rustdoc: correctly deal with self ty params when eliding default object lifetimes #115276
*  Stop emitting non-power-of-two vectors in (non-portable-SIMD) codegen #115236
*  Normalize before checking if local is freeze in deduced_param_attrs #114948

Some cherry-picks required merge conflict resolution, we'll see if I got it right based on CI (rustdoc fix and LLVM codegen test).

r? `@Mark-Simulacrum`

1 files changed, 4 insertions, 0 deletions

diff --git a/compiler/rustc_codegen_llvm/src/type_of.rs b/compiler/rustc_codegen_llvm/src/type_of.rs
index 58e97be34f2..7f7da8483ec 100644
--- a/compiler/rustc_codegen_llvm/src/type_of.rs
+++ b/compiler/rustc_codegen_llvm/src/type_of.rs
@@ -431,7 +431,11 @@ impl<'tcx> LayoutLlvmExt<'tcx> for TyAndLayout<'tcx> {
 
         // Vectors, even for non-power-of-two sizes, have the same layout as
         // arrays but don't count as aggregate types
+        // While LLVM theoretically supports non-power-of-two sizes, and they
+        // often work fine, sometimes x86-isel deals with them horribly
+        // (see #115212) so for now only use power-of-two ones.
         if let FieldsShape::Array { count, .. } = self.layout.fields()
+            && count.is_power_of_two()
             && let element = self.field(cx, 0)
             && element.ty.is_integral()
         {