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authorCaleb Zulawski <caleb.zulawski@gmail.com>2024-06-01 14:17:16 -0400
committerCaleb Zulawski <caleb.zulawski@gmail.com>2024-06-01 14:17:16 -0400
commit9bdc5b2455bbd8d71e912b5ceaeb390abb987c91 (patch)
tree0fb7f31d32954a88a59ecf9c4963e036a9c5b315 /compiler/rustc_codegen_llvm
parent86158f581d20948507bef65e6162e3bbf5f4fa91 (diff)
downloadrust-9bdc5b2455bbd8d71e912b5ceaeb390abb987c91.tar.gz
rust-9bdc5b2455bbd8d71e912b5ceaeb390abb987c91.zip
Improve documentation
Diffstat (limited to 'compiler/rustc_codegen_llvm')
-rw-r--r--compiler/rustc_codegen_llvm/src/intrinsic.rs7
1 files changed, 6 insertions, 1 deletions
diff --git a/compiler/rustc_codegen_llvm/src/intrinsic.rs b/compiler/rustc_codegen_llvm/src/intrinsic.rs
index 83a71752ffd..87098566f6b 100644
--- a/compiler/rustc_codegen_llvm/src/intrinsic.rs
+++ b/compiler/rustc_codegen_llvm/src/intrinsic.rs
@@ -480,10 +480,15 @@ impl<'ll, 'tcx> IntrinsicCallMethods<'tcx> for Builder<'_, 'll, 'tcx> {
             }
 
             _ if name.as_str().starts_with("simd_") => {
-                // Unpack non-power-of-2 #[repr(packed)]
+                // Unpack non-power-of-2 #[repr(packed, simd)] arguments.
+                // This gives them the expected layout of a regular #[repr(simd)] vector.
                 let mut loaded_args = Vec::new();
                 for (ty, arg) in arg_tys.iter().zip(args) {
                     loaded_args.push(
+                        // #[repr(packed, simd)] vectors are passed like arrays (as references,
+                        // with reduced alignment and no padding) rather than as immediates.
+                        // We can use a vector load to fix the layout and turn the argument
+                        // into an immediate.
                         if ty.is_simd()
                             && let OperandValue::Ref(place) = arg.val
                         {