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| author | bors <bors@rust-lang.org> | 2021-09-04 12:27:45 +0000 |
|---|---|---|
| committer | bors <bors@rust-lang.org> | 2021-09-04 12:27:45 +0000 |
| commit | 226e181b80fa0be755872b66916ef7e704601ec2 (patch) | |
| tree | 9c354d2143562358dd2dac4488cc14d7a71d95f0 /compiler/rustc_codegen_ssa/src | |
| parent | 72a51c39c69256c8a8256e775f2764a1983048d4 (diff) | |
| parent | 77a96ed5646f7c3ee8897693decc4626fe380643 (diff) | |
| download | rust-226e181b80fa0be755872b66916ef7e704601ec2.tar.gz rust-226e181b80fa0be755872b66916ef7e704601ec2.zip | |
Auto merge of #88550 - dpaoliello:dpaoliello/allocdebuginfo, r=estebank
Include debug info for the allocator shim Issue Details: In some cases it is necessary to generate an "allocator shim" to forward various Rust allocation functions (e.g., `__rust_alloc`) to an underlying function (e.g., `malloc`). However, since this allocator shim is a manually created LLVM module it is not processed via the normal module processing code and so no debug info is generated for it (if debugging info is enabled). Fix Details: * Modify the `debuginfo` code to allow creating debug info for a module without a `CodegenCx` (since it is difficult, and expensive, to create one just to emit some debug info). * After creating the allocator shim add in basic debug info.
Diffstat (limited to 'compiler/rustc_codegen_ssa/src')
| -rw-r--r-- | compiler/rustc_codegen_ssa/src/base.rs | 12 | ||||
| -rw-r--r-- | compiler/rustc_codegen_ssa/src/traits/backend.rs | 3 |
2 files changed, 11 insertions, 4 deletions
diff --git a/compiler/rustc_codegen_ssa/src/base.rs b/compiler/rustc_codegen_ssa/src/base.rs index a5143a755fe..f427dd76693 100644 --- a/compiler/rustc_codegen_ssa/src/base.rs +++ b/compiler/rustc_codegen_ssa/src/base.rs @@ -538,12 +538,18 @@ pub fn codegen_crate<B: ExtraBackendMethods>( } else if let Some(kind) = tcx.allocator_kind(()) { let llmod_id = cgu_name_builder.build_cgu_name(LOCAL_CRATE, &["crate"], Some("allocator")).to_string(); - let mut modules = backend.new_metadata(tcx, &llmod_id); + let mut module_llvm = backend.new_metadata(tcx, &llmod_id); tcx.sess.time("write_allocator_module", || { - backend.codegen_allocator(tcx, &mut modules, kind, tcx.lang_items().oom().is_some()) + backend.codegen_allocator( + tcx, + &mut module_llvm, + &llmod_id, + kind, + tcx.lang_items().oom().is_some(), + ) }); - Some(ModuleCodegen { name: llmod_id, module_llvm: modules, kind: ModuleKind::Allocator }) + Some(ModuleCodegen { name: llmod_id, module_llvm, kind: ModuleKind::Allocator }) } else { None }; diff --git a/compiler/rustc_codegen_ssa/src/traits/backend.rs b/compiler/rustc_codegen_ssa/src/traits/backend.rs index 1393fc71d6b..96e53f51dac 100644 --- a/compiler/rustc_codegen_ssa/src/traits/backend.rs +++ b/compiler/rustc_codegen_ssa/src/traits/backend.rs @@ -120,7 +120,8 @@ pub trait ExtraBackendMethods: CodegenBackend + WriteBackendMethods + Sized + Se fn codegen_allocator<'tcx>( &self, tcx: TyCtxt<'tcx>, - mods: &mut Self::Module, + module_llvm: &mut Self::Module, + module_name: &str, kind: AllocatorKind, has_alloc_error_handler: bool, ); |
