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| author | Michael Goulet <michael@errs.io> | 2023-06-02 16:02:06 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-06-02 16:02:06 -0700 |
| commit | 5460f92a0f97238e87fef281134b08deb2f587ee (patch) | |
| tree | cb108b149eb72261ac2ddd42adc1e42b4f82bb8b /compiler/rustc_codegen_ssa/src | |
| parent | dd09f4d35c5b6881f0eb757b5fd8c1604be3b06a (diff) | |
| parent | adb37d4999cbb83bd670bb767b3c8d08e43e3c7c (diff) | |
| download | rust-5460f92a0f97238e87fef281134b08deb2f587ee.tar.gz rust-5460f92a0f97238e87fef281134b08deb2f587ee.zip | |
Rollup merge of #112168 - scottmcm:lower-div-rem-unchecked-to-mir, r=oli-obk
Lower `unchecked_div`/`_rem` to MIR's `BinOp::Div`/`Rem` As described in <https://doc.rust-lang.org/nightly/nightly-rustc/rustc_middle/mir/enum.BinOp.html#variant.Div>, the ordinary `BinOp`s for these are already UB for division by zero ([or overflow](https://llvm.org/docs/LangRef.html#sdiv-instruction), [demo](https://rust.godbolt.org/z/71e7P7Exh)), as MIR building is responsible for inserting code to panic for those cases regardless of whether the overflow checks are enabled. So we can lower these in the same arm that lowers `wrapping_add` to MIR `BinOp::Add` and such, as all these cases turn into ordinary `Rvalue::BinaryOp`s.
Diffstat (limited to 'compiler/rustc_codegen_ssa/src')
| -rw-r--r-- | compiler/rustc_codegen_ssa/src/mir/intrinsic.rs | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs b/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs index 1479242f23a..9ac2424e76b 100644 --- a/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs +++ b/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs @@ -211,8 +211,6 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> { args[1].val.unaligned_volatile_store(bx, dst); return; } - | sym::unchecked_div - | sym::unchecked_rem | sym::unchecked_shl | sym::unchecked_shr | sym::unchecked_add @@ -229,20 +227,6 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> { bx.exactudiv(args[0].immediate(), args[1].immediate()) } } - sym::unchecked_div => { - if signed { - bx.sdiv(args[0].immediate(), args[1].immediate()) - } else { - bx.udiv(args[0].immediate(), args[1].immediate()) - } - } - sym::unchecked_rem => { - if signed { - bx.srem(args[0].immediate(), args[1].immediate()) - } else { - bx.urem(args[0].immediate(), args[1].immediate()) - } - } sym::unchecked_shl => bx.shl(args[0].immediate(), args[1].immediate()), sym::unchecked_shr => { if signed { |