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authorbors <bors@rust-lang.org>2023-06-02 23:02:42 +0000
committerbors <bors@rust-lang.org>2023-06-02 23:02:42 +0000
commit7a0070eaeadf6cd4641197401f0554bad12532eb (patch)
tree9e318c68a45ffbb209396b34288b23bfb9cceddb /compiler/rustc_codegen_ssa/src
parentdd5d7c729d4e8a59708df64002e09dbcbc4005ba (diff)
parent18763cb464e911a840ee5bd45093cd3fbadaf52d (diff)
downloadrust-7a0070eaeadf6cd4641197401f0554bad12532eb.tar.gz
rust-7a0070eaeadf6cd4641197401f0554bad12532eb.zip
Auto merge of #112228 - compiler-errors:rollup-97i0pli, r=compiler-errors
Rollup of 6 pull requests

Successful merges:

 - #109609 (Separate AnonConst from ConstBlock in HIR.)
 - #112166 (bootstrap: Rename profile = user to profile = dist)
 - #112168 (Lower `unchecked_div`/`_rem` to MIR's `BinOp::Div`/`Rem`)
 - #112183 (Normalize anon consts in new solver)
 - #112211 (pass `--lib` to `x doc`)
 - #112223 (Don't ICE in new solver when auto traits have associated types)

r? `@ghost`
`@rustbot` modify labels: rollup
Diffstat (limited to 'compiler/rustc_codegen_ssa/src')
-rw-r--r--compiler/rustc_codegen_ssa/src/mir/intrinsic.rs16
1 files changed, 0 insertions, 16 deletions
diff --git a/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs b/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs
index 1479242f23a..9ac2424e76b 100644
--- a/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs
+++ b/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs
@@ -211,8 +211,6 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> {
                 args[1].val.unaligned_volatile_store(bx, dst);
                 return;
             }
-            | sym::unchecked_div
-            | sym::unchecked_rem
             | sym::unchecked_shl
             | sym::unchecked_shr
             | sym::unchecked_add
@@ -229,20 +227,6 @@ impl<'a, 'tcx, Bx: BuilderMethods<'a, 'tcx>> FunctionCx<'a, 'tcx, Bx> {
                                 bx.exactudiv(args[0].immediate(), args[1].immediate())
                             }
                         }
-                        sym::unchecked_div => {
-                            if signed {
-                                bx.sdiv(args[0].immediate(), args[1].immediate())
-                            } else {
-                                bx.udiv(args[0].immediate(), args[1].immediate())
-                            }
-                        }
-                        sym::unchecked_rem => {
-                            if signed {
-                                bx.srem(args[0].immediate(), args[1].immediate())
-                            } else {
-                                bx.urem(args[0].immediate(), args[1].immediate())
-                            }
-                        }
                         sym::unchecked_shl => bx.shl(args[0].immediate(), args[1].immediate()),
                         sym::unchecked_shr => {
                             if signed {