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authorbors <bors@rust-lang.org>2023-03-15 21:31:06 +0000
committerbors <bors@rust-lang.org>2023-03-15 21:31:06 +0000
commitc90eb4825a9faca0d6317292a452859f00d5b786 (patch)
tree482fef868539e6bd9b3c955a3290efa6d0441fa4 /compiler/rustc_hir_analysis/src/astconv/mod.rs
parentab654863c3d50482f260cf862647f1fe0ff5e010 (diff)
parent0422f44dc475f60b9e9dbf5e0015abf9dcdffe44 (diff)
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Auto merge of #108282 - cjgillot:mir-checked-sh, r=tmiasko
Implement checked Shl/Shr at MIR building.

This does not require any special handling by codegen backends,
as the overflow behaviour is entirely determined by the rhs (shift amount).

This allows MIR ConstProp to remove the overflow check for constant shifts.

~There is an existing different behaviour between cg_llvm and cg_clif (cc `@bjorn3).`
I took cg_llvm's one as reference: overflow if `rhs < 0 || rhs > number_of_bits_in_lhs_ty`.~

EDIT: `cg_llvm` and `cg_clif` implement the overflow check differently. This PR uses `cg_llvm`'s implementation based on a `BitAnd` instead of `cg_clif`'s one based on an unsigned comparison.
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