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authorTsukasa OI <floss_rust@irq.a4lg.com>2025-03-24 00:23:46 +0000
committerTsukasa OI <floss_rust@irq.a4lg.com>2025-05-01 05:05:47 +0000
commiteec6cfb8dab2d20e58a44df0e1c52c5abf6b2d26 (patch)
treedb8b0f8fada53b6ec03d4aa7f1bc0d74724ba878 /compiler/rustc_llvm/src
parent0c33fe2c3d3eecadd17a84b110bb067288a64f1c (diff)
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rustc_target: RISC-V "Zfinx" is incompatible with {ILP32,LP64}[FD] ABIs
Because RISC-V Calling Conventions note that:

> This means code targeting the Zfinx extension always uses the ILP32,
> ILP32E or LP64 integer calling-convention only ABIs as there is no
> dedicated hardware floating-point register file.

{ILP32,LP64}[FD] ABIs with hardware floating-point calling conventions
are incompatible with the "Zfinx" extension.

This commit adds "zfinx" to the incompatible feature list to those ABIs
and tests whether trying to add "zdinx" (that is analogous to "zfinx" but
in double-precision) on a LP64D ABI configuration results in an error
(it also tests extension implication; "Zdinx" requires "Zfinx" extension).

Link: RISC-V psABI specification version 1.0
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0>
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