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| author | Chris Palmer <chris@noncombatant.org> | 2021-10-19 20:40:09 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-10-19 20:40:09 -0700 |
| commit | 3bb40f2ea00ceac3e91986a01ef5b2ecc8070f29 (patch) | |
| tree | e42ca131f893a269d8be668196380ff71f3af6d6 /compiler/rustc_mir_transform/src/coverage/debug.rs | |
| parent | 42983a28ab3c70728da7a9b932b667c978dd898d (diff) | |
| download | rust-3bb40f2ea00ceac3e91986a01ef5b2ecc8070f29.tar.gz rust-3bb40f2ea00ceac3e91986a01ef5b2ecc8070f29.zip | |
Make printed message match the code comment
I think this code is getting L0, not L1 cache size, if I'm reading the Intel manual right. (I might not be.) Either way, the code comment and the printed message should match, whichever way is right. :)
Diffstat (limited to 'compiler/rustc_mir_transform/src/coverage/debug.rs')
0 files changed, 0 insertions, 0 deletions