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authorScott McMurray <scottmcm@users.noreply.github.com>2023-06-03 00:41:50 -0700
committerScott McMurray <scottmcm@users.noreply.github.com>2023-06-19 01:47:03 -0700
commit39788e07bae91e9974ba6879a63e4e8b97503f5b (patch)
tree2b1d01608304f228b79e764cb41831c29dcfa604 /compiler/rustc_mir_transform/src/lower_intrinsics.rs
parent8d1fa473dddd12efb2430302e5f5dfcc3eb73f8b (diff)
downloadrust-39788e07bae91e9974ba6879a63e4e8b97503f5b.tar.gz
rust-39788e07bae91e9974ba6879a63e4e8b97503f5b.zip
Promote unchecked_add/sub/mul/shl/shr to mir::BinOp
Diffstat (limited to 'compiler/rustc_mir_transform/src/lower_intrinsics.rs')
-rw-r--r--compiler/rustc_mir_transform/src/lower_intrinsics.rs12
1 files changed, 11 insertions, 1 deletions
diff --git a/compiler/rustc_mir_transform/src/lower_intrinsics.rs b/compiler/rustc_mir_transform/src/lower_intrinsics.rs
index 3a7d58f7125..ce98e9b0c84 100644
--- a/compiler/rustc_mir_transform/src/lower_intrinsics.rs
+++ b/compiler/rustc_mir_transform/src/lower_intrinsics.rs
@@ -85,8 +85,13 @@ impl<'tcx> MirPass<'tcx> for LowerIntrinsics {
                     sym::wrapping_add
                     | sym::wrapping_sub
                     | sym::wrapping_mul
+                    | sym::unchecked_add
+                    | sym::unchecked_sub
+                    | sym::unchecked_mul
                     | sym::unchecked_div
-                    | sym::unchecked_rem => {
+                    | sym::unchecked_rem
+                    | sym::unchecked_shl
+                    | sym::unchecked_shr => {
                         let target = target.unwrap();
                         let lhs;
                         let rhs;
@@ -99,8 +104,13 @@ impl<'tcx> MirPass<'tcx> for LowerIntrinsics {
                             sym::wrapping_add => BinOp::Add,
                             sym::wrapping_sub => BinOp::Sub,
                             sym::wrapping_mul => BinOp::Mul,
+                            sym::unchecked_add => BinOp::AddUnchecked,
+                            sym::unchecked_sub => BinOp::SubUnchecked,
+                            sym::unchecked_mul => BinOp::MulUnchecked,
                             sym::unchecked_div => BinOp::Div,
                             sym::unchecked_rem => BinOp::Rem,
+                            sym::unchecked_shl => BinOp::ShlUnchecked,
+                            sym::unchecked_shr => BinOp::ShrUnchecked,
                             _ => bug!("unexpected intrinsic"),
                         };
                         block.statements.push(Statement {