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| author | Guillaume Gomez <guillaume1.gomez@gmail.com> | 2024-06-22 12:57:18 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-22 12:57:18 +0200 |
| commit | 07e8b3ac01b313e395f20b3000758ff60dd4d803 (patch) | |
| tree | 7f6b11d72ce3c023235c386f6cda64e27fbd87a5 /compiler/rustc_target/src/asm | |
| parent | f1b0d54ca9a5ea43950c279985a6e12dcf387de8 (diff) | |
| parent | 753fb070bb2962fc6f909c6d7adf568b6b28bbb5 (diff) | |
Rollup merge of #126555 - beetrees:f16-inline-asm-arm, r=Amanieu
Add `f16` inline ASM support for 32-bit ARM Adds `f16` inline ASM support for 32-bit ARM. SIMD vector types are taken from [here](https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:`@navigationhierarchiesreturnbasetype=[float]&f:@navigationhierarchieselementbitsize=[16]&f:@navigationhierarchiesarchitectures=[A32]).` Relevant issue: #125398 Tracking issue: #116909 `@rustbot` label +F-f16_and_f128
Diffstat (limited to 'compiler/rustc_target/src/asm')
| -rw-r--r-- | compiler/rustc_target/src/asm/arm.rs | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/compiler/rustc_target/src/asm/arm.rs b/compiler/rustc_target/src/asm/arm.rs index 37184393a73..9d79faadd61 100644 --- a/compiler/rustc_target/src/asm/arm.rs +++ b/compiler/rustc_target/src/asm/arm.rs @@ -47,16 +47,18 @@ impl ArmInlineAsmRegClass { _arch: InlineAsmArch, ) -> &'static [(InlineAsmType, Option<Symbol>)] { match self { - Self::reg => types! { _: I8, I16, I32, F32; }, - Self::sreg | Self::sreg_low16 => types! { vfp2: I32, F32; }, + Self::reg => types! { _: I8, I16, I32, F16, F32; }, + Self::sreg | Self::sreg_low16 => types! { vfp2: I32, F16, F32; }, Self::dreg_low16 | Self::dreg_low8 => types! { - vfp2: I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2); + vfp2: I64, F64; + neon: VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF16(4), VecF32(2); }, Self::dreg => types! { - d32: I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2); + d32: I64, F64; + neon: VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF16(4), VecF32(2); }, Self::qreg | Self::qreg_low8 | Self::qreg_low4 => types! { - neon: VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4); + neon: VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF16(8), VecF32(4); }, } } |