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authorTaiki Endo <te316e89@gmail.com>2024-11-29 03:01:33 +0900
committerTaiki Endo <te316e89@gmail.com>2024-11-29 03:01:33 +0900
commit0c8e36bb3052b217aebcd8bd2154cc31618caf4f (patch)
treee119ed5ce409c7d281f39f70735c56f086ba284c /compiler/rustc_target/src
parent9b4d7c6a40b328d212095c28670c629facf1557d (diff)
downloadrust-0c8e36bb3052b217aebcd8bd2154cc31618caf4f.tar.gz
rust-0c8e36bb3052b217aebcd8bd2154cc31618caf4f.zip
Fix target_feature handling in freg of LoongArch inline assembly
Diffstat (limited to 'compiler/rustc_target/src')
-rw-r--r--compiler/rustc_target/src/asm/loongarch.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/compiler/rustc_target/src/asm/loongarch.rs b/compiler/rustc_target/src/asm/loongarch.rs
index b1c01d27cad..b4ea6fc592a 100644
--- a/compiler/rustc_target/src/asm/loongarch.rs
+++ b/compiler/rustc_target/src/asm/loongarch.rs
@@ -38,7 +38,7 @@ impl LoongArchInlineAsmRegClass {
     ) -> &'static [(InlineAsmType, Option<Symbol>)] {
         match self {
             Self::reg => types! { _: I8, I16, I32, I64, F32, F64; },
-            Self::freg => types! { _: F32, F64; },
+            Self::freg => types! { f: F32; d: F64; },
         }
     }
 }