Auto merge of #126891 - matthiaskrgr:rollup-p6dl1gk, r=matthiaskrgr

Rollup of 9 pull requests

Successful merges:

 - #126177 (Add hard error and migration lint for unsafe attrs)
 - #126298 (Promote loongarch64-unknown-linux-musl to Tier 2 with host tools)
 - #126455 (For [E0308]: mismatched types, when expr is in an arm's body, not add semicolon ';' at the end of it.)
 - #126754 (Implement `use<>` formatting in rustfmt)
 - #126807 (std::unix::fs: copy simplification for apple.)
 - #126845 (Weekly `cargo update`)
 - #126849 (Fix 32-bit Arm reg classes by hierarchically sorting them)
 - #126854 (std::unix::os::home_dir: fallback's optimisation.)
 - #126888 (Remove stray println from rustfmt's `rewrite_static`)

r? `@ghost`
`@rustbot` modify labels: rollup

1 files changed, 40 insertions, 40 deletions

diff --git a/compiler/rustc_target/src/asm/arm.rs b/compiler/rustc_target/src/asm/arm.rs
index 9d79faadd61..70fcaab1847 100644
--- a/compiler/rustc_target/src/asm/arm.rs
+++ b/compiler/rustc_target/src/asm/arm.rs
@@ -148,22 +148,22 @@ def_regs! {
         r11: reg = ["r11", "fp"] % frame_pointer_r11,
         r12: reg = ["r12", "ip"] % not_thumb1,
         r14: reg = ["r14", "lr"] % not_thumb1,
-        s0: sreg, sreg_low16 = ["s0"],
-        s1: sreg, sreg_low16 = ["s1"],
-        s2: sreg, sreg_low16 = ["s2"],
-        s3: sreg, sreg_low16 = ["s3"],
-        s4: sreg, sreg_low16 = ["s4"],
-        s5: sreg, sreg_low16 = ["s5"],
-        s6: sreg, sreg_low16 = ["s6"],
-        s7: sreg, sreg_low16 = ["s7"],
-        s8: sreg, sreg_low16 = ["s8"],
-        s9: sreg, sreg_low16 = ["s9"],
-        s10: sreg, sreg_low16 = ["s10"],
-        s11: sreg, sreg_low16 = ["s11"],
-        s12: sreg, sreg_low16 = ["s12"],
-        s13: sreg, sreg_low16 = ["s13"],
-        s14: sreg, sreg_low16 = ["s14"],
-        s15: sreg, sreg_low16 = ["s15"],
+        s0: sreg_low16, sreg = ["s0"],
+        s1: sreg_low16, sreg = ["s1"],
+        s2: sreg_low16, sreg = ["s2"],
+        s3: sreg_low16, sreg = ["s3"],
+        s4: sreg_low16, sreg = ["s4"],
+        s5: sreg_low16, sreg = ["s5"],
+        s6: sreg_low16, sreg = ["s6"],
+        s7: sreg_low16, sreg = ["s7"],
+        s8: sreg_low16, sreg = ["s8"],
+        s9: sreg_low16, sreg = ["s9"],
+        s10: sreg_low16, sreg = ["s10"],
+        s11: sreg_low16, sreg = ["s11"],
+        s12: sreg_low16, sreg = ["s12"],
+        s13: sreg_low16, sreg = ["s13"],
+        s14: sreg_low16, sreg = ["s14"],
+        s15: sreg_low16, sreg = ["s15"],
         s16: sreg = ["s16"],
         s17: sreg = ["s17"],
         s18: sreg = ["s18"],
@@ -180,22 +180,22 @@ def_regs! {
         s29: sreg = ["s29"],
         s30: sreg = ["s30"],
         s31: sreg = ["s31"],
-        d0: dreg, dreg_low16, dreg_low8 = ["d0"],
-        d1: dreg, dreg_low16, dreg_low8 = ["d1"],
-        d2: dreg, dreg_low16, dreg_low8 = ["d2"],
-        d3: dreg, dreg_low16, dreg_low8 = ["d3"],
-        d4: dreg, dreg_low16, dreg_low8 = ["d4"],
-        d5: dreg, dreg_low16, dreg_low8 = ["d5"],
-        d6: dreg, dreg_low16, dreg_low8 = ["d6"],
-        d7: dreg, dreg_low16, dreg_low8 = ["d7"],
-        d8: dreg, dreg_low16 = ["d8"],
-        d9: dreg, dreg_low16 = ["d9"],
-        d10: dreg, dreg_low16 = ["d10"],
-        d11: dreg, dreg_low16 = ["d11"],
-        d12: dreg, dreg_low16 = ["d12"],
-        d13: dreg, dreg_low16 = ["d13"],
-        d14: dreg, dreg_low16 = ["d14"],
-        d15: dreg, dreg_low16 = ["d15"],
+        d0: dreg_low8, dreg_low16, dreg = ["d0"],
+        d1: dreg_low8, dreg_low16, dreg = ["d1"],
+        d2: dreg_low8, dreg_low16, dreg = ["d2"],
+        d3: dreg_low8, dreg_low16, dreg = ["d3"],
+        d4: dreg_low8, dreg_low16, dreg = ["d4"],
+        d5: dreg_low8, dreg_low16, dreg = ["d5"],
+        d6: dreg_low8, dreg_low16, dreg = ["d6"],
+        d7: dreg_low8, dreg_low16, dreg = ["d7"],
+        d8: dreg_low16, dreg = ["d8"],
+        d9: dreg_low16, dreg = ["d9"],
+        d10: dreg_low16, dreg = ["d10"],
+        d11: dreg_low16, dreg = ["d11"],
+        d12: dreg_low16, dreg = ["d12"],
+        d13: dreg_low16, dreg = ["d13"],
+        d14: dreg_low16, dreg = ["d14"],
+        d15: dreg_low16, dreg = ["d15"],
         d16: dreg = ["d16"],
         d17: dreg = ["d17"],
         d18: dreg = ["d18"],
@@ -212,14 +212,14 @@ def_regs! {
         d29: dreg = ["d29"],
         d30: dreg = ["d30"],
         d31: dreg = ["d31"],
-        q0: qreg, qreg_low8, qreg_low4 = ["q0"],
-        q1: qreg, qreg_low8, qreg_low4 = ["q1"],
-        q2: qreg, qreg_low8, qreg_low4 = ["q2"],
-        q3: qreg, qreg_low8, qreg_low4 = ["q3"],
-        q4: qreg, qreg_low8 = ["q4"],
-        q5: qreg, qreg_low8 = ["q5"],
-        q6: qreg, qreg_low8 = ["q6"],
-        q7: qreg, qreg_low8 = ["q7"],
+        q0: qreg_low4, qreg_low8, qreg = ["q0"],
+        q1: qreg_low4, qreg_low8, qreg = ["q1"],
+        q2: qreg_low4, qreg_low8, qreg = ["q2"],
+        q3: qreg_low4, qreg_low8, qreg = ["q3"],
+        q4: qreg_low8, qreg = ["q4"],
+        q5: qreg_low8, qreg = ["q5"],
+        q6: qreg_low8, qreg = ["q6"],
+        q7: qreg_low8, qreg = ["q7"],
         q8: qreg = ["q8"],
         q9: qreg = ["q9"],
         q10: qreg = ["q10"],