Auto merge of #134740 - Flakebi:amdgpu-target, r=workingjubilee

Add amdgpu target

Add amdgpu target to rustc and enable the LLVM target.

Fix compiling `core` with the amdgpu:
The amdgpu backend makes heavy use of different address spaces. This
leads to situations, where a pointer in one addrspace needs to be casted
to a pointer in a different addrspace. `bitcast` is invalid for this
case, `addrspacecast` needs to be used.

Fix compilation failures that created bitcasts for such cases by
creating pointer casts (which creates an `addrspacecast` under the hood)
instead.

MCP: https://github.com/rust-lang/compiler-team/issues/823
Tracking issue: #135024
Kinda related to the original amdgpu tracking issue #51575 (though that one has been closed for a while).

2 files changed, 53 insertions, 0 deletions

diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs
index 03b3426fcec..df1862ec27e 100644
--- a/compiler/rustc_target/src/spec/mod.rs
+++ b/compiler/rustc_target/src/spec/mod.rs
@@ -1934,6 +1934,8 @@ supported_targets! {
 
     ("nvptx64-nvidia-cuda", nvptx64_nvidia_cuda),
 
+    ("amdgcn-amd-amdhsa", amdgcn_amd_amdhsa),
+
     ("xtensa-esp32-none-elf", xtensa_esp32_none_elf),
     ("xtensa-esp32-espidf", xtensa_esp32_espidf),
     ("xtensa-esp32s2-none-elf", xtensa_esp32s2_none_elf),
diff --git a/compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs b/compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs
new file mode 100644
index 00000000000..bb488c350c2
--- /dev/null
+++ b/compiler/rustc_target/src/spec/targets/amdgcn_amd_amdhsa.rs
@@ -0,0 +1,51 @@
+use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, Target, TargetOptions};
+
+pub(crate) fn target() -> Target {
+    Target {
+        arch: "amdgpu".into(),
+        data_layout: "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9".into(),
+        llvm_target: "amdgcn-amd-amdhsa".into(),
+        metadata: crate::spec::TargetMetadata {
+            description: Some("AMD GPU".into()),
+            tier: Some(3),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 64,
+
+        options: TargetOptions {
+            os: "amdhsa".into(),
+            vendor: "amd".into(),
+            linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
+            linker: Some("rust-lld".into()),
+
+            // There are many CPUs, one for each hardware generation.
+            // Require to set one explicitly as there is no good default.
+            need_explicit_cpu: true,
+
+            max_atomic_width: Some(64),
+
+            // Unwinding on GPUs is not useful.
+            panic_strategy: PanicStrategy::Abort,
+
+            // amdgpu backend does not support libcalls.
+            no_builtins: true,
+            simd_types_indirect: false,
+
+            // Allow `cdylib` crate type.
+            dynamic_linking: true,
+            only_cdylib: true,
+            executables: false,
+            dll_prefix: "".into(),
+            dll_suffix: ".elf".into(),
+
+            // The LLVM backend does not support stack canaries for this target
+            supports_stack_protector: false,
+
+            // Force LTO, object linking does not yet work with amdgpu.
+            requires_lto: true,
+
+            ..Default::default()
+        },
+    }
+}