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authorMatthias Krüger <matthias.krueger@famsik.de>2023-06-06 12:00:32 +0200
committerGitHub <noreply@github.com>2023-06-06 12:00:32 +0200
commitc4e11dc3277ee44d4fbfb58da5273bd00940e6d4 (patch)
treef8620f228820300ce1b51ba4401f170dc6442dba /compiler
parent92327c05f1c54b403f3537a275baf469cdbe6632 (diff)
parent1f5361b40c4ccfa2f806cc9f293d8399a5651b9a (diff)
downloadrust-c4e11dc3277ee44d4fbfb58da5273bd00940e6d4.tar.gz
rust-c4e11dc3277ee44d4fbfb58da5273bd00940e6d4.zip
Rollup merge of #111369 - Nassiel:master, r=oli-obk
Added custom risc32-imac for esp-espidf target

ESP32-C6 and the upcoming ESP32-P4 are the first Espressif chips that support the "A" (atomic) extension of the RISCV specification.
As such, they do not work with the existing `riscv32imc-esp-espidf` target and instead need a new one (in this PR) called `riscv32imac-esp-espidf`.
Diffstat (limited to 'compiler')
-rw-r--r--compiler/rustc_target/src/spec/mod.rs1
-rw-r--r--compiler/rustc_target/src/spec/riscv32imac_esp_espidf.rs31
2 files changed, 32 insertions, 0 deletions
diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs
index 05cb7e87a93..99e4ba24afb 100644
--- a/compiler/rustc_target/src/spec/mod.rs
+++ b/compiler/rustc_target/src/spec/mod.rs
@@ -1284,6 +1284,7 @@ supported_targets! {
     ("riscv32im-unknown-none-elf", riscv32im_unknown_none_elf),
     ("riscv32imc-unknown-none-elf", riscv32imc_unknown_none_elf),
     ("riscv32imc-esp-espidf", riscv32imc_esp_espidf),
+    ("riscv32imac-esp-espidf", riscv32imac_esp_espidf),
     ("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),
     ("riscv32imac-unknown-xous-elf", riscv32imac_unknown_xous_elf),
     ("riscv32gc-unknown-linux-gnu", riscv32gc_unknown_linux_gnu),
diff --git a/compiler/rustc_target/src/spec/riscv32imac_esp_espidf.rs b/compiler/rustc_target/src/spec/riscv32imac_esp_espidf.rs
new file mode 100644
index 00000000000..0795065409a
--- /dev/null
+++ b/compiler/rustc_target/src/spec/riscv32imac_esp_espidf.rs
@@ -0,0 +1,31 @@
+use crate::spec::{cvs, PanicStrategy, RelocModel, Target, TargetOptions};
+
+pub fn target() -> Target {
+    Target {
+        data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
+        llvm_target: "riscv32".into(),
+        pointer_width: 32,
+        arch: "riscv32".into(),
+
+        options: TargetOptions {
+            families: cvs!["unix"],
+            os: "espidf".into(),
+            env: "newlib".into(),
+            vendor: "espressif".into(),
+            linker: Some("riscv32-esp-elf-gcc".into()),
+            cpu: "generic-rv32".into(),
+
+            // As RiscV32IMAC architecture does natively support atomics,
+            // automatically enable the support for the Rust STD library.
+            max_atomic_width: Some(64),
+            atomic_cas: true,
+
+            features: "+m,+a,+c".into(),
+            panic_strategy: PanicStrategy::Abort,
+            relocation_model: RelocModel::Static,
+            emit_debug_gdb_scripts: false,
+            eh_frame_header: false,
+            ..Default::default()
+        },
+    }
+}