RISC-V: Add two "A" extension subsets

The "A" extension comprises instructions provided by the "Zaamo" and
"Zalrsc" extensions.  To prepare for the "Zacas" extension (which provides
compare-and-swap instructions and discoverable from Linux) which depends on
the "Zaamo" extension, it would be better to support those subsets.

2 files changed, 10 insertions, 1 deletions

diff --git a/library/stdarch/crates/std_detect/src/detect/arch/riscv.rs b/library/stdarch/crates/std_detect/src/detect/arch/riscv.rs
index 29d8da8e122..271700aefa6 100644
--- a/library/stdarch/crates/std_detect/src/detect/arch/riscv.rs
+++ b/library/stdarch/crates/std_detect/src/detect/arch/riscv.rs
@@ -30,6 +30,8 @@ features! {
     /// * RV32I: `"rv32i"`
     /// * RV64I: `"rv64i"`
     /// * A: `"a"`
+    ///   * Zaamo: `"zaamo"`
+    ///   * Zalrsc: `"zalrsc"`
     /// * Bit-Manipulation Extensions:
     ///   * Zba: `"zba"`
     ///   * Zbb: `"zbb"`
@@ -122,6 +124,10 @@ features! {
 
     @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] a: "a";
     /// "A" Extension for Atomic Instructions
+    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zalrsc: "zalrsc";
+    /// "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
+    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zaamo: "zaamo";
+    /// "Zaamo" Extension for Atomic Memory Operations
     @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
     without cfg check: true;
     /// "Zam" Extension for Misaligned Atomics
diff --git a/library/stdarch/crates/std_detect/src/detect/os/linux/riscv.rs b/library/stdarch/crates/std_detect/src/detect/os/linux/riscv.rs
index ee74c7c29aa..33deba93355 100644
--- a/library/stdarch/crates/std_detect/src/detect/os/linux/riscv.rs
+++ b/library/stdarch/crates/std_detect/src/detect/os/linux/riscv.rs
@@ -18,7 +18,10 @@ pub(crate) fn detect_features() -> cache::Initializer {
     // [hwcap]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/include/uapi/asm/hwcap.h?h=v6.14
     let auxv = auxvec::auxv().expect("read auxvec"); // should not fail on RISC-V platform
     #[allow(clippy::eq_op)]
-    enable_feature(Feature::a, bit::test(auxv.hwcap, (b'a' - b'a').into()));
+    let has_a = bit::test(auxv.hwcap, (b'a' - b'a').into());
+    enable_feature(Feature::a, has_a);
+    enable_feature(Feature::zalrsc, has_a);
+    enable_feature(Feature::zaamo, has_a);
     enable_feature(Feature::c, bit::test(auxv.hwcap, (b'c' - b'a').into()));
     let has_d = bit::test(auxv.hwcap, (b'd' - b'a').into());
     let has_f = bit::test(auxv.hwcap, (b'f' - b'a').into());