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| author | Gijs Burghoorn <g.burghoorn@gmail.com> | 2023-08-15 13:56:49 +0200 |
|---|---|---|
| committer | Amanieu d'Antras <amanieu@gmail.com> | 2023-08-31 23:12:32 +0200 |
| commit | 992bd5e1a9ebc6243d52ca9931bfebfc3e5bbe8e (patch) | |
| tree | 86040bfb5722f4ac823a9dca14c1cd01a034a596 /library/stdarch/crates | |
| parent | 1c5eb32416c241a30389446351d8ee01b837e1b2 (diff) | |
| download | rust-992bd5e1a9ebc6243d52ca9931bfebfc3e5bbe8e.tar.gz rust-992bd5e1a9ebc6243d52ca9931bfebfc3e5bbe8e.zip | |
Fix: Assembly mistakes in RISC-V Zk extensions
Diffstat (limited to 'library/stdarch/crates')
| -rw-r--r-- | library/stdarch/crates/core_arch/src/riscv32/zk.rs | 6 | ||||
| -rw-r--r-- | library/stdarch/crates/core_arch/src/riscv64/zk.rs | 4 | ||||
| -rw-r--r-- | library/stdarch/crates/core_arch/src/riscv_shared/zk.rs | 4 |
3 files changed, 7 insertions, 7 deletions
diff --git a/library/stdarch/crates/core_arch/src/riscv32/zk.rs b/library/stdarch/crates/core_arch/src/riscv32/zk.rs index d95890f420f..81bcd0d2dfc 100644 --- a/library/stdarch/crates/core_arch/src/riscv32/zk.rs +++ b/library/stdarch/crates/core_arch/src/riscv32/zk.rs @@ -142,9 +142,6 @@ pub unsafe fn aes32dsi(rs1: u32, rs2: u32, bs: u8) -> u32 { constify_imm2!(bs, aes32dsi) } -#[target_feature(enable = "zknd")] -#[cfg_attr(test, assert_instr(aes32dsmi))] -#[inline] /// AES middle round decryption instruction for RV32. /// /// This instruction sources a single byte from rs2 according to bs. To this it applies the @@ -166,6 +163,9 @@ pub unsafe fn aes32dsi(rs1: u32, rs2: u32, bs: u8) -> u32 { /// # Safety /// /// This function is safe to use if the `zknd` target feature is present. +#[target_feature(enable = "zknd")] +#[cfg_attr(test, assert_instr(aes32dsmi))] +#[inline] pub unsafe fn aes32dsmi(rs1: u32, rs2: u32, bs: u8) -> u32 { macro_rules! aes32dsmi { ($imm2:expr) => {{ diff --git a/library/stdarch/crates/core_arch/src/riscv64/zk.rs b/library/stdarch/crates/core_arch/src/riscv64/zk.rs index de45ad62c7d..8f2884668ab 100644 --- a/library/stdarch/crates/core_arch/src/riscv64/zk.rs +++ b/library/stdarch/crates/core_arch/src/riscv64/zk.rs @@ -142,7 +142,7 @@ pub unsafe fn aes64dsm(rs1: u64, rs2: u64) -> u64 { let value: u64; unsafe { asm!( - "aes64esm {rd},{rs1},{rs2}", + "aes64dsm {rd},{rs1},{rs2}", rd = lateout(reg) value, rs1 = in(reg) rs1, rs2 = in(reg) rs2, @@ -378,7 +378,7 @@ pub unsafe fn sha512sum1(rs1: u64) -> u64 { let value: u64; unsafe { asm!( - "sha512sum0 {rd},{rs1}", + "sha512sum1 {rd},{rs1}", rd = lateout(reg) value, rs1 = in(reg) rs1, options(pure, nomem, nostack), diff --git a/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs b/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs index 37ae597b8aa..8402c267567 100644 --- a/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs +++ b/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs @@ -267,7 +267,7 @@ pub unsafe fn sha256sum0(rs1: usize) -> usize { let value: usize; unsafe { asm!( - "sha256sig1 {rd},{rs1}", + "sha256sum0 {rd},{rs1}", rd = lateout(reg) value, rs1 = in(reg) rs1, options(pure, nomem, nostack), @@ -302,7 +302,7 @@ pub unsafe fn sha256sum1(rs1: usize) -> usize { let value: usize; unsafe { asm!( - "sha256sig1 {rd},{rs1}", + "sha256sum1 {rd},{rs1}", rd = lateout(reg) value, rs1 = in(reg) rs1, options(pure, nomem, nostack), |