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| author | Ralf Jung <post@ralfj.de> | 2019-04-13 09:13:43 +0200 |
|---|---|---|
| committer | gnzlbg <gnzlbg@users.noreply.github.com> | 2019-04-14 08:43:33 +0200 |
| commit | d2b8c78afbd0dcab7c88d1094efbed62d81e4892 (patch) | |
| tree | 2914547f8e74f4f1badfcd3c3cb6e4ec496d3ab7 /library/stdarch/crates | |
| parent | f3414889afeee7fed1c20a9fc20d04c6abc2d2d9 (diff) | |
| download | rust-d2b8c78afbd0dcab7c88d1094efbed62d81e4892.tar.gz rust-d2b8c78afbd0dcab7c88d1094efbed62d81e4892.zip | |
fix rustdoc link failures
Diffstat (limited to 'library/stdarch/crates')
| -rw-r--r-- | library/stdarch/crates/core_arch/src/acle/dsp.rs | 50 | ||||
| -rw-r--r-- | library/stdarch/crates/core_arch/src/acle/simd32.rs | 118 |
2 files changed, 84 insertions, 84 deletions
diff --git a/library/stdarch/crates/core_arch/src/acle/dsp.rs b/library/stdarch/crates/core_arch/src/acle/dsp.rs index d1bd4c85849..5572f50d7ec 100644 --- a/library/stdarch/crates/core_arch/src/acle/dsp.rs +++ b/library/stdarch/crates/core_arch/src/acle/dsp.rs @@ -4,21 +4,21 @@ //! //! Intrinsics that could live here: //! -//! - [x] __smulbb -//! - [x] __smulbt -//! - [x] __smultb -//! - [x] __smultt -//! - [x] __smulwb -//! - [x] __smulwt -//! - [x] __qadd -//! - [x] __qsub -//! - [x] __qdbl -//! - [x] __smlabb -//! - [x] __smlabt -//! - [x] __smlatb -//! - [x] __smlatt -//! - [x] __smlawb -//! - [x] __smlawt +//! - \[x\] __smulbb +//! - \[x\] __smulbt +//! - \[x\] __smultb +//! - \[x\] __smultt +//! - \[x\] __smulwb +//! - \[x\] __smulwt +//! - \[x\] __qadd +//! - \[x\] __qsub +//! - \[x\] __qdbl +//! - \[x\] __smlabb +//! - \[x\] __smlabt +//! - \[x\] __smlatb +//! - \[x\] __smlatt +//! - \[x\] __smlawb +//! - \[x\] __smlawt #[cfg(test)] use stdsimd_test::assert_instr; @@ -99,7 +99,7 @@ pub unsafe fn __smultb(a: int16x2_t, b: int16x2_t) -> i32 { /// Insert a SMULTB instruction /// /// Returns the equivalent of a\[1\] * b\[0\] -/// where [0] is the lower 16 bits and [1] is the upper 16 bits. +/// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits. #[inline] #[cfg_attr(test, assert_instr(smulbt))] pub unsafe fn __smulbt(a: int16x2_t, b: int16x2_t) -> i32 { @@ -109,7 +109,7 @@ pub unsafe fn __smulbt(a: int16x2_t, b: int16x2_t) -> i32 { /// Insert a SMULTT instruction /// /// Returns the equivalent of a\[1\] * b\[1\] -/// where [0] is the lower 16 bits and [1] is the upper 16 bits. +/// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits. #[inline] #[cfg_attr(test, assert_instr(smultt))] pub unsafe fn __smultt(a: int16x2_t, b: int16x2_t) -> i32 { @@ -171,7 +171,7 @@ pub unsafe fn __qdbl(a: i32) -> i32 { /// Insert a SMLABB instruction /// /// Returns the equivalent of a\[0\] * b\[0\] + c -/// where [0] is the lower 16 bits and [1] is the upper 16 bits. +/// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits. /// Sets the Q flag if overflow occurs on the addition. #[inline] #[cfg_attr(test, assert_instr(smlabb))] @@ -182,7 +182,7 @@ pub unsafe fn __smlabb(a: int16x2_t, b: int16x2_t, c: i32) -> i32 { /// Insert a SMLABT instruction /// /// Returns the equivalent of a\[0\] * b\[1\] + c -/// where [0] is the lower 16 bits and [1] is the upper 16 bits. +/// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits. /// Sets the Q flag if overflow occurs on the addition. #[inline] #[cfg_attr(test, assert_instr(smlabt))] @@ -193,7 +193,7 @@ pub unsafe fn __smlabt(a: int16x2_t, b: int16x2_t, c: i32) -> i32 { /// Insert a SMLATB instruction /// /// Returns the equivalent of a\[1\] * b\[0\] + c -/// where [0] is the lower 16 bits and [1] is the upper 16 bits. +/// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits. /// Sets the Q flag if overflow occurs on the addition. #[inline] #[cfg_attr(test, assert_instr(smlatb))] @@ -204,7 +204,7 @@ pub unsafe fn __smlatb(a: int16x2_t, b: int16x2_t, c: i32) -> i32 { /// Insert a SMLATT instruction /// /// Returns the equivalent of a\[1\] * b\[1\] + c -/// where [0] is the lower 16 bits and [1] is the upper 16 bits. +/// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits. /// Sets the Q flag if overflow occurs on the addition. #[inline] #[cfg_attr(test, assert_instr(smlatt))] @@ -214,8 +214,8 @@ pub unsafe fn __smlatt(a: int16x2_t, b: int16x2_t, c: i32) -> i32 { /// Insert a SMLAWB instruction /// -/// Returns the equivalent of (a * b[0] + (c << 16)) >> 16 -/// where [0] is the lower 16 bits and [1] is the upper 16 bits. +/// Returns the equivalent of (a * b\[0\] + (c << 16)) >> 16 +/// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits. /// Sets the Q flag if overflow occurs on the addition. #[inline] #[cfg_attr(test, assert_instr(smlawb))] @@ -225,8 +225,8 @@ pub unsafe fn __smlawb(a: i32, b: int16x2_t, c: i32) -> i32 { /// Insert a SMLAWT instruction /// -/// Returns the equivalent of (a * b[1] + (c << 16)) >> 16 -/// where [0] is the lower 16 bits and [1] is the upper 16 bits. +/// Returns the equivalent of (a * b\[1\] + (c << 16)) >> 16 +/// where \[0\] is the lower 16 bits and \[1\] is the upper 16 bits. /// Sets the Q flag if overflow occurs on the addition. #[inline] #[cfg_attr(test, assert_instr(smlawt))] diff --git a/library/stdarch/crates/core_arch/src/acle/simd32.rs b/library/stdarch/crates/core_arch/src/acle/simd32.rs index 32cf2d2c352..f53c5d632ec 100644 --- a/library/stdarch/crates/core_arch/src/acle/simd32.rs +++ b/library/stdarch/crates/core_arch/src/acle/simd32.rs @@ -4,63 +4,63 @@ //! //! Intrinsics that could live here //! -//! - [x] __sel -//! - [ ] __ssat16 -//! - [ ] __usat16 -//! - [ ] __sxtab16 -//! - [ ] __sxtb16 -//! - [ ] __uxtab16 -//! - [ ] __uxtb16 -//! - [x] __qadd8 -//! - [x] __qsub8 -//! - [x] __sadd8 -//! - [x] __shadd8 -//! - [x] __shsub8 -//! - [x] __ssub8 -//! - [ ] __uadd8 -//! - [ ] __uhadd8 -//! - [ ] __uhsub8 -//! - [ ] __uqadd8 -//! - [ ] __uqsub8 -//! - [x] __usub8 -//! - [x] __usad8 -//! - [x] __usada8 -//! - [x] __qadd16 -//! - [x] __qasx -//! - [x] __qsax -//! - [x] __qsub16 -//! - [x] __sadd16 -//! - [x] __sasx -//! - [x] __shadd16 -//! - [ ] __shasx -//! - [ ] __shsax -//! - [x] __shsub16 -//! - [ ] __ssax -//! - [ ] __ssub16 -//! - [ ] __uadd16 -//! - [ ] __uasx -//! - [ ] __uhadd16 -//! - [ ] __uhasx -//! - [ ] __uhsax -//! - [ ] __uhsub16 -//! - [ ] __uqadd16 -//! - [ ] __uqasx -//! - [x] __uqsax -//! - [ ] __uqsub16 -//! - [ ] __usax -//! - [ ] __usub16 -//! - [x] __smlad -//! - [ ] __smladx -//! - [ ] __smlald -//! - [ ] __smlaldx -//! - [x] __smlsd -//! - [ ] __smlsdx -//! - [ ] __smlsld -//! - [ ] __smlsldx -//! - [x] __smuad -//! - [x] __smuadx -//! - [x] __smusd -//! - [x] __smusdx +//! - \[x\] __sel +//! - \[ \] __ssat16 +//! - \[ \] __usat16 +//! - \[ \] __sxtab16 +//! - \[ \] __sxtb16 +//! - \[ \] __uxtab16 +//! - \[ \] __uxtb16 +//! - \[x\] __qadd8 +//! - \[x\] __qsub8 +//! - \[x\] __sadd8 +//! - \[x\] __shadd8 +//! - \[x\] __shsub8 +//! - \[x\] __ssub8 +//! - \[ \] __uadd8 +//! - \[ \] __uhadd8 +//! - \[ \] __uhsub8 +//! - \[ \] __uqadd8 +//! - \[ \] __uqsub8 +//! - \[x\] __usub8 +//! - \[x\] __usad8 +//! - \[x\] __usada8 +//! - \[x\] __qadd16 +//! - \[x\] __qasx +//! - \[x\] __qsax +//! - \[x\] __qsub16 +//! - \[x\] __sadd16 +//! - \[x\] __sasx +//! - \[x\] __shadd16 +//! - \[ \] __shasx +//! - \[ \] __shsax +//! - \[x\] __shsub16 +//! - \[ \] __ssax +//! - \[ \] __ssub16 +//! - \[ \] __uadd16 +//! - \[ \] __uasx +//! - \[ \] __uhadd16 +//! - \[ \] __uhasx +//! - \[ \] __uhsax +//! - \[ \] __uhsub16 +//! - \[ \] __uqadd16 +//! - \[ \] __uqasx +//! - \[x\] __uqsax +//! - \[ \] __uqsub16 +//! - \[ \] __usax +//! - \[ \] __usub16 +//! - \[x\] __smlad +//! - \[ \] __smladx +//! - \[ \] __smlald +//! - \[ \] __smlaldx +//! - \[x\] __smlsd +//! - \[ \] __smlsdx +//! - \[ \] __smlsld +//! - \[ \] __smlsldx +//! - \[x\] __smuad +//! - \[x\] __smuadx +//! - \[x\] __smusd +//! - \[x\] __smusdx #[cfg(test)] use stdsimd_test::assert_instr; @@ -349,7 +349,7 @@ pub unsafe fn __shsub8(a: int8x4_t, b: int8x4_t) -> int8x4_t { /// res\[2\] = a\[2\] - a\[2\] /// res\[3\] = a\[3\] - a\[3\] /// -/// where [0] is the lower 8 bits and [3] is the upper 8 bits. +/// where \[0\] is the lower 8 bits and \[3\] is the upper 8 bits. /// The GE bits of the APSR are set. #[inline] #[cfg_attr(test, assert_instr(usub8))] @@ -366,7 +366,7 @@ pub unsafe fn __usub8(a: uint8x4_t, b: uint8x4_t) -> uint8x4_t { /// res\[2\] = a\[2\] - a\[2\] /// res\[3\] = a\[3\] - a\[3\] /// -/// where [0] is the lower 8 bits and [3] is the upper 8 bits. +/// where \[0\] is the lower 8 bits and \[3\] is the upper 8 bits. /// The GE bits of the APSR are set. #[inline] #[cfg_attr(test, assert_instr(ssub8))] |
