PR feedback & pipeline

21 files changed, 124 insertions, 357 deletions

diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
index 08f7aecdb62..cedc0c458b0 100644
--- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
@@ -7953,7 +7953,7 @@ pub unsafe fn vcvts_n_f32_u32<const N: i32>(a: u32) -> f32 {
 #[rustc_legacy_const_generics(1)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub unsafe fn vcvtd_n_f64_u64<const N: i32>(a: u64) -> f64 {
-    static_assert!(N >= 1 && N <= 32);
+    static_assert!(N >= 1 && N <= 64);
     extern "unadjusted" {
         #[cfg_attr(
             any(target_arch = "aarch64", target_arch = "arm64ec"),
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
index e89067142b3..09be5282e9e 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -15227,7 +15227,7 @@ pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) ->
             size: i32,
         ) -> float32x2x4_t;
     }
-    vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
+    _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
 }
 
 #[doc = "Load multiple 4-element structures to four registers"]
@@ -15254,7 +15254,7 @@ pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -
             size: i32,
         ) -> float32x4x4_t;
     }
-    vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
+    _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
 }
 
 #[doc = "Load multiple 4-element structures to four registers"]
@@ -15281,7 +15281,7 @@ pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8
             size: i32,
         ) -> int8x8x4_t;
     }
-    vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
+    _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
 }
 
 #[doc = "Load multiple 4-element structures to four registers"]
@@ -15308,7 +15308,7 @@ pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> i
             size: i32,
         ) -> int16x4x4_t;
     }
-    vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
+    _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
 }
 
 #[doc = "Load multiple 4-element structures to four registers"]
@@ -15335,7 +15335,7 @@ pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) ->
             size: i32,
         ) -> int16x8x4_t;
     }
-    vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
+    _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
 }
 
 #[doc = "Load multiple 4-element structures to four registers"]
@@ -15362,7 +15362,7 @@ pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> i
             size: i32,
         ) -> int32x2x4_t;
     }
-    vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
+    _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
 }
 
 #[doc = "Load multiple 4-element structures to four registers"]
@@ -15389,7 +15389,7 @@ pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) ->
             size: i32,
         ) -> int32x4x4_t;
     }
-    vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
+    _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
 }
 
 #[doc = "Load multiple 4-element structures to four registers"]
@@ -25928,7 +25928,7 @@ pub unsafe fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
     }
     _vqrshrn_n_s32(
         a,
-        const { int16x8_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
+        const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
     )
 }
 
@@ -25948,7 +25948,7 @@ pub unsafe fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")]
         fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
     }
-    _vqrshrn_n_s64(a, const { int16x8_t([-N as i64, -N as i64]) })
+    _vqrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) })
 }
 
 #[doc = "Signed saturating rounded shift right narrow"]
@@ -26033,15 +26033,17 @@ pub unsafe fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")]
         fn _vqrshrn_n_u16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
     }
-    _vqrshrnq_n_u16(
+    _vqrshrn_n_u16(
         a.as_signed(),
         const {
             uint16x8_t([
                 -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
                 -N as u16,
             ])
-        },
+        }
+        .as_signed(),
     )
+    .as_unsigned()
 }
 
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
@@ -26060,10 +26062,11 @@ pub unsafe fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")]
         fn _vqrshrn_n_u32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
     }
-    _vqrshrnq_n_u32(
+    _vqrshrn_n_u32(
         a.as_signed(),
-        const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
+        const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }.as_signed(),
     )
+    .as_unsigned()
 }
 
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
@@ -26082,7 +26085,11 @@ pub unsafe fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")]
         fn _vqrshrn_n_u64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
     }
-    _vqrshrnq_n_u64(a.as_signed(), const { uint64x2_t([-N as u64, -N as u64]) })
+    _vqrshrn_n_u64(
+        a.as_signed(),
+        const { uint64x2_t([-N as u64, -N as u64]) }.as_signed(),
+    )
+    .as_unsigned()
 }
 
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
@@ -26162,14 +26169,7 @@ pub unsafe fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 pub unsafe fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
-    static_assert!(
-        const {
-            int16x8_t([
-                -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
-                -N as i16,
-            ])
-        }
-    );
+    static_assert!(N >= 1 && N <= 8);
     extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")]
         fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
@@ -26197,7 +26197,7 @@ pub unsafe fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 pub unsafe fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
-    static_assert!(const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) });
+    static_assert!(N >= 1 && N <= 16);
     extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")]
         fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
@@ -26220,7 +26220,7 @@ pub unsafe fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 #[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
 pub unsafe fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
-    static_assert!(const { int64x2_t([-N as i64, -N as i64]) });
+    static_assert!(N >= 1 && N <= 32);
     extern "unadjusted" {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")]
         fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
@@ -27773,7 +27773,8 @@ pub unsafe fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
                 -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
                 -N as u16,
             ])
-        },
+        }
+        .as_signed(),
     )
     .as_unsigned()
 }
@@ -27796,7 +27797,7 @@ pub unsafe fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
     }
     _vqshrn_n_u32(
         a.as_signed(),
-        const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
+        const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }.as_signed(),
     )
     .as_unsigned()
 }
@@ -27817,7 +27818,11 @@ pub unsafe fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")]
         fn _vqshrn_n_u64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
     }
-    _vqshrn_n_u64(a.as_signed(), const { uint64x2_t([-N as u64, -N as u64]) }).as_unsigned()
+    _vqshrn_n_u64(
+        a.as_signed(),
+        const { uint64x2_t([-N as u64, -N as u64]) }.as_signed(),
+    )
+    .as_unsigned()
 }
 
 #[doc = "Unsigned saturating shift right narrow"]
@@ -27902,7 +27907,7 @@ pub unsafe fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")]
         fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
     }
-    _vqshrun_n_u8(
+    _vqshrun_n_s16(
         a,
         const {
             int16x8_t([
@@ -27911,6 +27916,7 @@ pub unsafe fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
             ])
         },
     )
+    .as_unsigned()
 }
 
 #[doc = "Signed saturating shift right unsigned narrow"]
@@ -27929,10 +27935,11 @@ pub unsafe fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")]
         fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
     }
-    _vqshrun_n_u16(
+    _vqshrun_n_s32(
         a,
         const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
     )
+    .as_unsigned()
 }
 
 #[doc = "Signed saturating shift right unsigned narrow"]
@@ -27951,7 +27958,7 @@ pub unsafe fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")]
         fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
     }
-    _vqshrun_n_u32(a, const { int64x2_t([-N as i64, -N as i64]) })
+    _vqshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }).as_unsigned()
 }
 
 #[doc = "Signed saturating shift right unsigned narrow"]
@@ -43688,7 +43695,7 @@ pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v2f32")]
         fn _vst2_lane_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, n: i32, size: i32);
     }
-    _vst2_f32(a as _, b.0, b.1, LANE, 4)
+    _vst2_lane_f32(a as _, b.0, b.1, LANE, 4)
 }
 
 #[doc = "Store multiple 2-element structures from two registers"]
@@ -43707,7 +43714,7 @@ pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4f32")]
         fn _vst2q_lane_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, n: i32, size: i32);
     }
-    _vst2q_f32(a as _, b.0, b.1, LANE, 4)
+    _vst2q_lane_f32(a as _, b.0, b.1, LANE, 4)
 }
 
 #[doc = "Store multiple 2-element structures from two registers"]
@@ -43726,7 +43733,7 @@ pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v8i8")]
         fn _vst2_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32);
     }
-    _vst2_s8(a as _, b.0, b.1, LANE, 1)
+    _vst2_lane_s8(a as _, b.0, b.1, LANE, 1)
 }
 
 #[doc = "Store multiple 2-element structures from two registers"]
@@ -43745,7 +43752,7 @@ pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4i16")]
         fn _vst2_lane_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, n: i32, size: i32);
     }
-    _vst2_s16(a as _, b.0, b.1, LANE, 2)
+    _vst2_lane_s16(a as _, b.0, b.1, LANE, 2)
 }
 
 #[doc = "Store multiple 2-element structures from two registers"]
@@ -43764,7 +43771,7 @@ pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v8i16")]
         fn _vst2q_lane_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, n: i32, size: i32);
     }
-    _vst2q_s16(a as _, b.0, b.1, LANE, 2)
+    _vst2q_lane_s16(a as _, b.0, b.1, LANE, 2)
 }
 
 #[doc = "Store multiple 2-element structures from two registers"]
@@ -43783,7 +43790,7 @@ pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v2i32")]
         fn _vst2_lane_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, n: i32, size: i32);
     }
-    _vst2_s32(a as _, b.0, b.1, LANE, 4)
+    _vst2_lane_s32(a as _, b.0, b.1, LANE, 4)
 }
 
 #[doc = "Store multiple 2-element structures from two registers"]
@@ -43802,7 +43809,7 @@ pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4i32")]
         fn _vst2q_lane_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, n: i32, size: i32);
     }
-    _vst2q_s32(a as _, b.0, b.1, LANE, 4)
+    _vst2q_lane_s32(a as _, b.0, b.1, LANE, 4)
 }
 
 #[doc = "Store multiple 2-element structures from two registers"]
@@ -44657,7 +44664,7 @@ pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
             size: i32,
         );
     }
-    _vst3_f32(a as _, b.0, b.1, b.2, LANE, 4)
+    _vst3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
 }
 
 #[doc = "Store multiple 3-element structures from three registers"]
@@ -44683,7 +44690,7 @@ pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
             size: i32,
         );
     }
-    _vst3q_f32(a as _, b.0, b.1, b.2, LANE, 4)
+    _vst3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
 }
 
 #[doc = "Store multiple 3-element structures from three registers"]
@@ -44702,7 +44709,7 @@ pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i8")]
         fn _vst3_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i32, size: i32);
     }
-    _vst3_s8(a as _, b.0, b.1, b.2, LANE, 1)
+    _vst3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1)
 }
 
 #[doc = "Store multiple 3-element structures from three registers"]
@@ -44728,7 +44735,7 @@ pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
             size: i32,
         );
     }
-    _vst3_s16(a as _, b.0, b.1, b.2, LANE, 2)
+    _vst3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
 }
 
 #[doc = "Store multiple 3-element structures from three registers"]
@@ -44754,7 +44761,7 @@ pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
             size: i32,
         );
     }
-    _vst3q_s16(a as _, b.0, b.1, b.2, LANE, 2)
+    _vst3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
 }
 
 #[doc = "Store multiple 3-element structures from three registers"]
@@ -44780,7 +44787,7 @@ pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
             size: i32,
         );
     }
-    _vst3_s32(a as _, b.0, b.1, b.2, LANE, 4)
+    _vst3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
 }
 
 #[doc = "Store multiple 3-element structures from three registers"]
@@ -44806,7 +44813,7 @@ pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
             size: i32,
         );
     }
-    _vst3q_s32(a as _, b.0, b.1, b.2, LANE, 4)
+    _vst3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
 }
 
 #[doc = "Store multiple 3-element structures from three registers"]
@@ -45865,7 +45872,7 @@ pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
             size: i32,
         );
     }
-    _vst4_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
+    _vst4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
 }
 
 #[doc = "Store multiple 4-element structures from four registers"]
@@ -45892,7 +45899,7 @@ pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
             size: i32,
         );
     }
-    _vst4q_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
+    _vst4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
 }
 
 #[doc = "Store multiple 4-element structures from four registers"]
@@ -45919,7 +45926,7 @@ pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
             size: i32,
         );
     }
-    _vst4_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
+    _vst4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
 }
 
 #[doc = "Store multiple 4-element structures from four registers"]
@@ -45946,7 +45953,7 @@ pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
             size: i32,
         );
     }
-    _vst4_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
+    _vst4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
 }
 
 #[doc = "Store multiple 4-element structures from four registers"]
@@ -45973,7 +45980,7 @@ pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
             size: i32,
         );
     }
-    _vst4q_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
+    _vst4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
 }
 
 #[doc = "Store multiple 4-element structures from four registers"]
@@ -46000,7 +46007,7 @@ pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
             size: i32,
         );
     }
-    _vst4_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
+    _vst4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
 }
 
 #[doc = "Store multiple 4-element structures from four registers"]
@@ -46027,7 +46034,7 @@ pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
             size: i32,
         );
     }
-    _vst4q_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
+    _vst4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
 }
 
 #[doc = "Store multiple 4-element structures from four registers"]
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs
index 52707f527dc..fe5f8361e02 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs
@@ -11,89 +11,33 @@ use crate::{core_arch::simd::*, hint::unreachable_unchecked, intrinsics::simd::*
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
-#[unstable(feature = "stdarch_internal", issue = "none")]
 pub(crate) trait AsUnsigned {
     type Unsigned: ?Sized;
-    unsafe fn as_unsigned(self) -> Self::Unsigned;
+    fn as_unsigned(self) -> Self::Unsigned;
 }
 
-#[unstable(feature = "stdarch_internal", issue = "none")]
 pub(crate) trait AsSigned {
     type Signed: ?Sized;
-    unsafe fn as_signed(self) -> Self::Signed;
-}
-
-macro_rules! impl_sign_conversions {
-    ($(($signed:ty, $unsigned:ty))*) => ($(
-        #[cfg_attr(
-            not(target_arch = "arm"),
-            stable(feature = "neon_intrinsics", since = "1.59.0")
-        )]
-        #[cfg_attr(
-            target_arch = "arm",
-            unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-        )]
-        impl AsUnsigned for $signed {
-            type Unsigned = $unsigned;
-
-            #[inline]
-            unsafe fn as_unsigned(self) -> $unsigned {
-                crate::mem::transmute(self)
-            }
-        }
-
-        #[cfg_attr(
-            not(target_arch = "arm"),
-            stable(feature = "neon_intrinsics", since = "1.59.0")
-        )]
-        #[cfg_attr(
-            target_arch = "arm",
-            unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-        )]
-        impl AsSigned for $unsigned {
-            type Signed = $signed;
-
-            #[inline]
-            unsafe fn as_signed(self) -> $signed {
-                crate::mem::transmute(self)
-            }
-        }
-    )*)
+    fn as_signed(self) -> Self::Signed;
 }
 
 macro_rules! impl_sign_conversions_neon {
     ($(($signed:ty, $unsigned:ty))*) => ($(
-        #[cfg_attr(
-            not(target_arch = "arm"),
-            stable(feature = "neon_intrinsics", since = "1.59.0")
-        )]
-        #[cfg_attr(
-            target_arch = "arm",
-            unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-        )]
         impl AsUnsigned for $signed {
             type Unsigned = $unsigned;
 
             #[inline]
-            unsafe fn as_unsigned(self) -> $unsigned {
-                crate::mem::transmute(self)
+            fn as_unsigned(self) -> $unsigned {
+                unsafe { transmute(self) }
             }
         }
 
-        #[cfg_attr(
-            not(target_arch = "arm"),
-            stable(feature = "neon_intrinsics", since = "1.59.0")
-        )]
-        #[cfg_attr(
-            target_arch = "arm",
-            unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
-        )]
         impl AsSigned for $unsigned {
             type Signed = $signed;
 
             #[inline]
-            unsafe fn as_signed(self) -> $signed {
-                crate::mem::transmute(self)
+            fn as_signed(self) -> $signed {
+                unsafe { transmute(self) }
             }
         }
     )*)
@@ -1121,7 +1065,7 @@ pub struct poly64x2x4_t(
     pub poly64x2_t,
 );
 
-impl_sign_conversions! {
+impl_sign_conversions_neon! {
     (i8, u8)
     (i16, u16)
     (i32, u32)
@@ -1150,9 +1094,6 @@ impl_sign_conversions! {
     (uint64x2_t, int64x2_t)
     (uint8x16_t, int8x16_t)
     (uint8x8_t, int8x8_t)
-}
-
-impl_sign_conversions_neon! {
     (int16x4x2_t, uint16x4x2_t)
     (int16x4x3_t, uint16x4x3_t)
     (int16x4x4_t, uint16x4x4_t)
diff --git a/library/stdarch/crates/stdarch-gen2/Cargo.toml b/library/stdarch/crates/stdarch-gen-arm/Cargo.toml
index c9a039ea6b7..3cc49825492 100644
--- a/library/stdarch/crates/stdarch-gen2/Cargo.toml
+++ b/library/stdarch/crates/stdarch-gen-arm/Cargo.toml
@@ -1,10 +1,11 @@
 [package]
-name = "stdarch-gen2"
+name = "stdarch-gen-arm"
 version = "0.1.0"
 authors = ["Luca Vizzarro <luca.vizzarro@arm.com>",
         "Jamie Cunliffe <Jamie.Cunliffe@arm.com>",
         "Adam Gemmell <Adam.Gemmell@arm.com",
-        "Jacob Bramley <jacob.bramley@arm.com>"]
+        "Jacob Bramley <jacob.bramley@arm.com>",
+        "James Barford-Evans <james.barford-evans@arm.com>"]
 license = "MIT OR Apache-2.0"
 edition = "2021"
 
diff --git a/library/stdarch/crates/stdarch-gen2/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index fd704c305e3..6f622b18be8 100644
--- a/library/stdarch/crates/stdarch-gen2/spec/neon/aarch64.spec.yml
+++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -1089,7 +1089,7 @@ intrinsics:
       - ["u32", "f32", 's_n_f32_u32', 'N >= 1 && N <= 32']
       - ["u64", "f64", 'd_n_f64_u64', 'N >= 1 && N <= 64']
     compose:
-      - FnCall: [static_assert!, ['N >= 1 && N <= 32']]
+      - FnCall: [static_assert!, ["{type[3]}"]]
       - LLVMLink:
           name: "vcvt{type[2]}"
           arguments:
diff --git a/library/stdarch/crates/stdarch-gen2/spec/neon/arm_shared.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index 87559963ed1..a3c26a709b8 100644
--- a/library/stdarch/crates/stdarch-gen2/spec/neon/arm_shared.spec.yml
+++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -3687,7 +3687,7 @@ intrinsics:
           links:
             - link: 'llvm.arm.neon.vld4lane.v{neon_type[1].lane}{type[3]}.p0i8'
               arch: arm
-      - FnCall: ['vld4{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', LANE, '{type[4]}']]
+      - FnCall: ['_vld4{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', LANE, '{type[4]}']]
 
   - name: "vld4{neon_type[1].lane_nox}"
     doc: Load multiple 4-element structures to four registers
@@ -4323,7 +4323,7 @@ intrinsics:
           links:
             - link: 'llvm.arm.neon.vst2lane.p0i8.v{neon_type[1].lane}{type[0]}'
               arch: arm
-      - FnCall: ['_vst2{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'LANE', "{type[4]}"]]
+      - FnCall: ['_vst2{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'LANE', "{type[4]}"]]
 
   - name: "vst3{neon_type[1].nox}"
     doc: "Store multiple 3-element structures from three registers"
@@ -4538,7 +4538,7 @@ intrinsics:
           links:
             - link: 'llvm.arm.neon.vst3lane.p0i8.v{neon_type[1].lane}{type[0]}'
               arch: arm
-      - FnCall: ['_vst3{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'LANE', "{type[4]}"]]
+      - FnCall: ['_vst3{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'LANE', "{type[4]}"]]
 
   - name: "vst3{neon_type[1].nox}"
     doc: "Store multiple 3-element structures from three registers"
@@ -4820,7 +4820,7 @@ intrinsics:
           links:
             - link: 'llvm.arm.neon.vst4lane.p0i8.v{neon_type[1].lane}{type[0]}'
               arch: arm
-      - FnCall: ['_vst4{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', 'LANE', "{type[4]}"]]
+      - FnCall: ['_vst4{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', 'LANE', "{type[4]}"]]
 
   - name: "vst4{neon_type[1].nox}"
     doc: "Store multiple 4-element structures from four registers"
@@ -6473,8 +6473,8 @@ intrinsics:
       unsafe: [neon]
     types:
       - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }']
-      - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int16x8_t([-N as i32, -N as i32, -N as i32, -N as i32]) }']
-      - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int16x8_t([-N as i64, -N as i64]) }']
+      - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }']
+      - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }']
     compose:
       - FnCall: [static_assert!, ["{type[2]}"]]
       - LLVMLink:
@@ -6533,7 +6533,7 @@ intrinsics:
       - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }']
       - [int64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }']
     compose:
-      - FnCall: [static_assert!, ["{type[3]}"]]
+      - FnCall: [static_assert!, ["{type[2]}"]]
       - LLVMLink:
           name: "vqrshrun_n{neon_type[0].noq}"
           arguments:
@@ -6766,9 +6766,9 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }']
-      - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }']
-      - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { uint64x2_t([-N as u64, -N as u64]) }']
+      - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }.as_signed()']
+      - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }.as_signed()']
+      - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { uint64x2_t([-N as u64, -N as u64]) }.as_signed()']
     compose:
       - FnCall: [static_assert!, ["{type[2]}"]]
       - LLVMLink:
@@ -6836,7 +6836,7 @@ intrinsics:
           links:
             - link: "llvm.arm.neon.vqshiftnsu.{neon_type[1]}"
               arch: arm
-      - FnCall: ["_vqshrun_n_{neon_type[1]}", [a, "{type[3]}"]]
+      - FnCall: ["_vqshrun_n_{neon_type[0]}", [a, "{type[3]}"]]
 
   - name: "vqshrun_n_{neon_type[0]}"
     doc: "Signed saturating shift right unsigned narrow"
@@ -8784,9 +8784,9 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }']
-      - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }']
-      - [uint64x2_t, uint32x2_t, '32', 'const { uint64x2_t([-N as u64, -N as u64]) }']
+      - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }.as_signed()']
+      - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }.as_signed()']
+      - [uint64x2_t, uint32x2_t, '32', 'const { uint64x2_t([-N as u64, -N as u64]) }.as_signed()']
     compose:
       - FnCall: [static_assert!, ['N >= 1 && N <= {type[2]}']]
       - LLVMLink:
@@ -8797,7 +8797,7 @@ intrinsics:
           links:
             - link: "llvm.arm.neon.vqrshiftnu.{neon_type[1]}"
               arch: arm
-      - FnCall: ["_vqrshrn{neon_type[0].N}", ["a.as_signed()", "{type[3]}"]]
+      - FnCall: ["_vqrshrn_n{neon_type[0].noq}", ["a.as_signed()", "{type[3]}"]]
 
   - name: "vqrshrn_n_{neon_type[0]}"
     doc: "Unsigned signed saturating rounded shift right narrow"
diff --git a/library/stdarch/crates/stdarch-gen2/src/assert_instr.rs b/library/stdarch/crates/stdarch-gen-arm/src/assert_instr.rs
index ce1bbe8b55f..ce1bbe8b55f 100644
--- a/library/stdarch/crates/stdarch-gen2/src/assert_instr.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/assert_instr.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/context.rs b/library/stdarch/crates/stdarch-gen-arm/src/context.rs
index 8405428b7ad..8405428b7ad 100644
--- a/library/stdarch/crates/stdarch-gen2/src/context.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/context.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/expression.rs b/library/stdarch/crates/stdarch-gen-arm/src/expression.rs
index 83984679588..83984679588 100644
--- a/library/stdarch/crates/stdarch-gen2/src/expression.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/expression.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/fn_suffix.rs b/library/stdarch/crates/stdarch-gen-arm/src/fn_suffix.rs
index 9f7827776e0..9f7827776e0 100644
--- a/library/stdarch/crates/stdarch-gen2/src/fn_suffix.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/fn_suffix.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/input.rs b/library/stdarch/crates/stdarch-gen-arm/src/input.rs
index bb2414adec2..bb2414adec2 100644
--- a/library/stdarch/crates/stdarch-gen2/src/input.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/input.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/intrinsic.rs b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs
index 4a973691b17..4a973691b17 100644
--- a/library/stdarch/crates/stdarch-gen2/src/intrinsic.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/load_store_tests.rs b/library/stdarch/crates/stdarch-gen-arm/src/load_store_tests.rs
index d697a8d22d6..d697a8d22d6 100644
--- a/library/stdarch/crates/stdarch-gen2/src/load_store_tests.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/load_store_tests.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/main.rs b/library/stdarch/crates/stdarch-gen-arm/src/main.rs
index 22bf6724b02..22bf6724b02 100644
--- a/library/stdarch/crates/stdarch-gen2/src/main.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/main.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/matching.rs b/library/stdarch/crates/stdarch-gen-arm/src/matching.rs
index 0c480620428..0c480620428 100644
--- a/library/stdarch/crates/stdarch-gen2/src/matching.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/matching.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/predicate_forms.rs b/library/stdarch/crates/stdarch-gen-arm/src/predicate_forms.rs
index 02789bf7eb0..02789bf7eb0 100644
--- a/library/stdarch/crates/stdarch-gen2/src/predicate_forms.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/predicate_forms.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/typekinds.rs b/library/stdarch/crates/stdarch-gen-arm/src/typekinds.rs
index 7a4fed85ce7..7a4fed85ce7 100644
--- a/library/stdarch/crates/stdarch-gen2/src/typekinds.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/typekinds.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/wildcards.rs b/library/stdarch/crates/stdarch-gen-arm/src/wildcards.rs
index 25aa8034892..25aa8034892 100644
--- a/library/stdarch/crates/stdarch-gen2/src/wildcards.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/wildcards.rs
diff --git a/library/stdarch/crates/stdarch-gen2/src/wildstring.rs b/library/stdarch/crates/stdarch-gen-arm/src/wildstring.rs
index 2eb467b9628..2eb467b9628 100644
--- a/library/stdarch/crates/stdarch-gen2/src/wildstring.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/wildstring.rs
diff --git a/library/stdarch/crates/stdarch-verify/src/lib.rs b/library/stdarch/crates/stdarch-verify/src/lib.rs
index c53f1e62975..5e4db96a70d 100644
--- a/library/stdarch/crates/stdarch-verify/src/lib.rs
+++ b/library/stdarch/crates/stdarch-verify/src/lib.rs
@@ -45,9 +45,7 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream {
     for &mut (ref mut file, ref path) in &mut files {
         for mut item in file.items.drain(..) {
             match item {
-                syn::Item::Fn(f) => {
-                    functions.push((f, path));
-                }
+                syn::Item::Fn(f) => functions.push((f, path)),
                 syn::Item::Mod(ref mut m) => {
                     if let Some(ref mut m) = m.content {
                         for i in m.1.drain(..) {
@@ -73,9 +71,12 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream {
     assert!(!tests.is_empty());
 
     functions.retain(|(f, _)| {
-        matches!(f.vis, syn::Visibility::Public(_))
-            // Many SVE intrinsics are safe
-            && (f.sig.unsafety.is_some() || f.sig.ident.to_string().starts_with("sv"))
+        if let syn::Visibility::Public(_) = f.vis {
+            if f.sig.unsafety.is_some() {
+                return true;
+            }
+        }
+        false
     });
     assert!(!functions.is_empty());
 
@@ -98,7 +99,7 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream {
             for generic in f.sig.generics.params.iter() {
                 match *generic {
                     syn::GenericParam::Const(ref c) => const_arguments.push(to_type(&c.ty)),
-                    syn::GenericParam::Type(_) => (),
+                    syn::GenericParam::Type(ref _t) => (),
                     _ => panic!("invalid generic argument on {name}"),
                 };
             }
@@ -117,31 +118,25 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream {
             };
 
             let required_const = find_required_const("rustc_args_required_const", &f.attrs);
-            let mut const_generics_indices =
+            let mut legacy_const_generics =
                 find_required_const("rustc_legacy_const_generics", &f.attrs);
-            if !required_const.is_empty() && !const_generics_indices.is_empty() {
+            if !required_const.is_empty() && !legacy_const_generics.is_empty() {
                 panic!(
                     "Can't have both #[rustc_args_required_const] and \
                      #[rustc_legacy_const_generics]"
                 );
             }
 
-            // Newer intrinsics don't have legacy support - assume they belong at the end of the argument list
-            if required_const.is_empty() && const_generics_indices.is_empty() {
-                const_generics_indices =
-                    (arguments.len()..(arguments.len() + const_arguments.len())).collect();
-            }
-
             // The list of required consts, used to verify the arguments, comes from either the
             // `rustc_args_required_const` or the `rustc_legacy_const_generics` attribute.
             let required_const = if required_const.is_empty() {
-                const_generics_indices.clone()
+                legacy_const_generics.clone()
             } else {
                 required_const
             };
 
-            const_generics_indices.sort();
-            for (idx, ty) in const_generics_indices
+            legacy_const_generics.sort();
+            for (idx, ty) in legacy_const_generics
                 .into_iter()
                 .zip(const_arguments.into_iter())
             {
@@ -150,12 +145,12 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream {
 
             // strip leading underscore from fn name when building a test
             // _mm_foo -> mm_foo such that the test name is test_mm_foo.
-            let test_name = name.to_string();
-            let test_name_id = test_name.trim_start_matches('_');
-            let has_test = tests.contains(&format!("test_{test_name_id}"))
-                // SVE load/store tests
-                || tests.iter().any(|t| t.starts_with(&format!("test_{test_name_id}"))
-                                        || t.ends_with(&format!("_with_{test_name_id}")));
+            let test_name_string = format!("{name}");
+            let mut test_name_id = test_name_string.as_str();
+            while test_name_id.starts_with('_') {
+                test_name_id = &test_name_id[1..];
+            }
+            let has_test = tests.contains(&format!("test_{test_name_id}"));
 
             let doc = find_doc(&f.attrs);
 
@@ -226,53 +221,8 @@ fn to_type(t: &syn::Type) -> proc_macro2::TokenStream {
             "p16" => quote! { &P16 },
             "Ordering" => quote! { &ORDERING },
             "CpuidResult" => quote! { &CPUID },
-            "T" => quote! { &GENERICT },
 
             // arm ...
-            "svbool_t" => quote! { &SVBOOL },
-            "svint8_t" => quote! { &SVI8 },
-            "svint8x2_t" => quote! { &SVI8X2 },
-            "svint8x3_t" => quote! { &SVI8X3 },
-            "svint8x4_t" => quote! { &SVI8X4 },
-            "svint16_t" => quote! { &SVI16 },
-            "svint16x2_t" => quote! { &SVI16X2 },
-            "svint16x3_t" => quote! { &SVI16X3 },
-            "svint16x4_t" => quote! { &SVI16X4 },
-            "svint32_t" => quote! { &SVI32 },
-            "svint32x2_t" => quote! { &SVI32X2 },
-            "svint32x3_t" => quote! { &SVI32X3 },
-            "svint32x4_t" => quote! { &SVI32X4 },
-            "svint64_t" => quote! { &SVI64 },
-            "svint64x2_t" => quote! { &SVI64X2 },
-            "svint64x3_t" => quote! { &SVI64X3 },
-            "svint64x4_t" => quote! { &SVI64X4 },
-            "svuint8_t" => quote! { &SVU8 },
-            "svuint8x2_t" => quote! { &SVU8X2 },
-            "svuint8x3_t" => quote! { &SVU8X3 },
-            "svuint8x4_t" => quote! { &SVU8X4 },
-            "svuint16_t" => quote! { &SVU16 },
-            "svuint16x2_t" => quote! { &SVU16X2 },
-            "svuint16x3_t" => quote! { &SVU16X3 },
-            "svuint16x4_t" => quote! { &SVU16X4 },
-            "svuint32_t" => quote! { &SVU32 },
-            "svuint32x2_t" => quote! { &SVU32X2 },
-            "svuint32x3_t" => quote! { &SVU32X3 },
-            "svuint32x4_t" => quote! { &SVU32X4 },
-            "svuint64_t" => quote! { &SVU64 },
-            "svuint64x2_t" => quote! { &SVU64X2 },
-            "svuint64x3_t" => quote! { &SVU64X3 },
-            "svuint64x4_t" => quote! { &SVU64X4 },
-            "svfloat32_t" => quote! { &SVF32 },
-            "svfloat32x2_t" => quote! { &SVF32X2 },
-            "svfloat32x3_t" => quote! { &SVF32X3 },
-            "svfloat32x4_t" => quote! { &SVF32X4 },
-            "svfloat64_t" => quote! { &SVF64 },
-            "svfloat64x2_t" => quote! { &SVF64X2 },
-            "svfloat64x3_t" => quote! { &SVF64X3 },
-            "svfloat64x4_t" => quote! { &SVF64X4 },
-            "svprfop" => quote! { &SVPRFOP },
-            "svpattern" => quote! { &SVPATTERN },
-
             "int8x4_t" => quote! { &I8X4 },
             "int8x8_t" => quote! { &I8X8 },
             "int8x8x2_t" => quote! { &I8X8X2 },
diff --git a/library/stdarch/crates/stdarch-verify/tests/arm.rs b/library/stdarch/crates/stdarch-verify/tests/arm.rs
index fe51a6730cf..a35b8175fb2 100644
--- a/library/stdarch/crates/stdarch-verify/tests/arm.rs
+++ b/library/stdarch/crates/stdarch-verify/tests/arm.rs
@@ -27,8 +27,6 @@ static U16: Type = Type::PrimUnsigned(16);
 static U32: Type = Type::PrimUnsigned(32);
 static U64: Type = Type::PrimUnsigned(64);
 static U8: Type = Type::PrimUnsigned(8);
-static BOOL: Type = Type::PrimBool;
-static VOID: Type = Type::Void;
 static NEVER: Type = Type::Never;
 static GENERICT: Type = Type::GenericParam("T");
 static GENERICU: Type = Type::GenericParam("U");
@@ -153,70 +151,19 @@ static U8X8X2: Type = Type::U(8, 8, 2);
 static U8X8X3: Type = Type::U(8, 8, 3);
 static U8X8X4: Type = Type::U(8, 8, 4);
 
-static SVBOOL: Type = Type::Pred;
-static SVF32: Type = Type::SVF(32, 1);
-static SVF32X2: Type = Type::SVF(32, 2);
-static SVF32X3: Type = Type::SVF(32, 3);
-static SVF32X4: Type = Type::SVF(32, 4);
-static SVF64: Type = Type::SVF(64, 1);
-static SVF64X2: Type = Type::SVF(64, 2);
-static SVF64X3: Type = Type::SVF(64, 3);
-static SVF64X4: Type = Type::SVF(64, 4);
-static SVI8: Type = Type::SVI(8, 1);
-static SVI8X2: Type = Type::SVI(8, 2);
-static SVI8X3: Type = Type::SVI(8, 3);
-static SVI8X4: Type = Type::SVI(8, 4);
-static SVI16: Type = Type::SVI(16, 1);
-static SVI16X2: Type = Type::SVI(16, 2);
-static SVI16X3: Type = Type::SVI(16, 3);
-static SVI16X4: Type = Type::SVI(16, 4);
-static SVI32: Type = Type::SVI(32, 1);
-static SVI32X2: Type = Type::SVI(32, 2);
-static SVI32X3: Type = Type::SVI(32, 3);
-static SVI32X4: Type = Type::SVI(32, 4);
-static SVI64: Type = Type::SVI(64, 1);
-static SVI64X2: Type = Type::SVI(64, 2);
-static SVI64X3: Type = Type::SVI(64, 3);
-static SVI64X4: Type = Type::SVI(64, 4);
-static SVU8: Type = Type::SVU(8, 1);
-static SVU8X2: Type = Type::SVU(8, 2);
-static SVU8X3: Type = Type::SVU(8, 3);
-static SVU8X4: Type = Type::SVU(8, 4);
-static SVU16: Type = Type::SVU(16, 1);
-static SVU16X2: Type = Type::SVU(16, 2);
-static SVU16X3: Type = Type::SVU(16, 3);
-static SVU16X4: Type = Type::SVU(16, 4);
-static SVU32: Type = Type::SVU(32, 1);
-static SVU32X2: Type = Type::SVU(32, 2);
-static SVU32X3: Type = Type::SVU(32, 3);
-static SVU32X4: Type = Type::SVU(32, 4);
-static SVU64: Type = Type::SVU(64, 1);
-static SVU64X2: Type = Type::SVU(64, 2);
-static SVU64X3: Type = Type::SVU(64, 3);
-static SVU64X4: Type = Type::SVU(64, 4);
-static SVPRFOP: Type = Type::Enum("svprfop");
-static SVPATTERN: Type = Type::Enum("svpattern");
-
 #[derive(Debug, Copy, Clone, PartialEq)]
 enum Type {
-    Void,
-    PrimBool,
     PrimFloat(u8),
     PrimSigned(u8),
     PrimUnsigned(u8),
     PrimPoly(u8),
     MutPtr(&'static Type),
     ConstPtr(&'static Type),
-    Enum(&'static str),
     GenericParam(&'static str),
     I(u8, u8, u8),
     U(u8, u8, u8),
     P(u8, u8, u8),
     F(u8, u8, u8),
-    Pred,
-    SVI(u8, u8),
-    SVU(u8, u8),
-    SVF(u8, u8),
     Never,
 }
 
@@ -235,7 +182,6 @@ fn verify_all_signatures() {
 
     let mut all_valid = true;
     for rust in FUNCTIONS {
-        // Most SVE intrinsics just rely on the intrinsics test tool for validation
         if !rust.has_test {
             let skip = [
                 "vaddq_s64",
@@ -461,18 +407,6 @@ fn verify_all_signatures() {
                 "__clrex",
                 "__dbg",
             ];
-            if !skip.contains(&rust.name)
-                // Most run-time tests are handled by the intrinsic-test tool, except for
-                // load/stores (which have generated tests)
-                && (!rust.name.starts_with("sv") || rust.name.starts_with("svld")
-                    || rust.name.starts_with("svst"))
-                // The load/store test generator can't handle these cases yet
-                && (!rust.name.contains("_u32base_") || rust.name.contains("index") || rust.name.contains("offset"))
-                && !(rust.name.starts_with("svldff1") && rust.name.contains("gather"))
-            {
-                println!("missing run-time test for `{}`", rust.name);
-                all_valid = false;
-            }
         }
 
         // Skip some intrinsics that aren't NEON and are located in different
@@ -545,21 +479,12 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> {
     let mut nconst = 0;
     let iter = rust.arguments.iter().zip(&arm.arguments).enumerate();
     for (i, (rust_ty, (arm, arm_const))) in iter {
-        match (*rust_ty, arm) {
-            // SVE uses generic type parameters to handle void pointers
-            (Type::ConstPtr(Type::GenericParam("T")), Type::ConstPtr(Type::Void)) => (),
-            // SVE const generics use i32 over u64 for usability reasons
-            (Type::PrimSigned(32), Type::PrimUnsigned(64)) if rust.required_const.contains(&i) => {
-                ()
-            }
-            // svset doesn't have its const argument last as we assumed when building the Function
-            _ if rust.name.starts_with("svset") => (),
-            (x, y) if x == y => (),
-            _ => bail!("mismatched arguments: {rust_ty:?} != {arm:?}"),
+        if *rust_ty != arm {
+            bail!("mismatched arguments: {rust_ty:?} != {arm:?}")
         }
         if *arm_const {
             nconst += 1;
-            if !rust.required_const.contains(&i) && !rust.name.starts_with("svset") {
+            if !rust.required_const.contains(&i) {
                 bail!("argument const mismatch");
             }
         }
@@ -568,7 +493,7 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> {
         bail!("wrong number of const arguments");
     }
 
-    if rust.instrs.is_empty() && arm.instruction != "" {
+    if rust.instrs.is_empty() {
         bail!(
             "instruction not listed for `{}`, but arm lists {:?}",
             rust.name,
@@ -607,7 +532,7 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> {
     Ok(())
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(PartialEq)]
 struct Intrinsic {
     name: String,
     ret: Option<Type>,
@@ -622,7 +547,7 @@ struct JsonIntrinsic {
     arguments: Vec<String>,
     return_type: ReturnType,
     #[serde(default)]
-    instructions: Option<Vec<Vec<String>>>,
+    instructions: Vec<Vec<String>>,
 }
 
 #[derive(Deserialize, Debug)]
@@ -639,8 +564,8 @@ fn parse_intrinsics(intrinsics: Vec<JsonIntrinsic>) -> HashMap<String, Intrinsic
     ret
 }
 
-fn parse_intrinsic(intr: JsonIntrinsic) -> Intrinsic {
-    let name = intr.name.replace('[', "").replace(']', "");
+fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic {
+    let name = intr.name;
     let ret = if intr.return_type.value == "void" {
         None
     } else {
@@ -649,24 +574,18 @@ fn parse_intrinsic(intr: JsonIntrinsic) -> Intrinsic {
 
     // This ignores multiple instructions and different optional sequences for now to mimic
     // the old HTML scraping behaviour
-    let instruction = intr
-        .instructions
-        .map_or(String::new(), |mut i| i.swap_remove(0).swap_remove(0));
+    let instruction = intr.instructions.swap_remove(0).swap_remove(0);
 
     let arguments = intr
         .arguments
         .iter()
         .map(|s| {
-            let ty = if let Some(i) = s.find('*') {
-                &s[..i + 1]
-            } else {
-                s.rsplit_once(' ').unwrap().0.trim_start_matches("const ")
+            let (ty, konst) = match s.strip_prefix("const") {
+                Some(stripped) => (stripped.trim_start(), true),
+                None => (s.as_str(), false),
             };
-            let ty = parse_ty(ty);
-            let konst = s.contains("const") && !matches!(ty, Type::ConstPtr(_))
-                || s.starts_with("enum")
-                || s.rsplit_once(" ").unwrap().1.starts_with("imm");
-            (ty, konst)
+            let ty = ty.rsplit_once(' ').unwrap().0;
+            (parse_ty(ty), konst)
         })
         .collect::<Vec<_>>();
 
@@ -679,26 +598,18 @@ fn parse_intrinsic(intr: JsonIntrinsic) -> Intrinsic {
 }
 
 fn parse_ty(s: &str) -> Type {
-    if let Some(ty) = s.strip_suffix("*") {
-        let ty = ty.trim();
-        if let Some(ty) = ty.strip_prefix("const") {
-            // SVE intrinsics are west-const (const int8_t *)
-            Type::ConstPtr(parse_ty_base(ty))
-        } else if let Some(ty) = ty.strip_suffix("const") {
-            // Neon intrinsics are east-const (int8_t const *)
-            Type::ConstPtr(parse_ty_base(ty))
-        } else {
-            Type::MutPtr(parse_ty_base(ty))
-        }
+    let suffix = " const *";
+    if let Some(base) = s.strip_suffix(suffix) {
+        Type::ConstPtr(parse_ty_base(base))
+    } else if let Some(base) = s.strip_suffix(" *") {
+        Type::MutPtr(parse_ty_base(base))
     } else {
         *parse_ty_base(s)
     }
 }
 
 fn parse_ty_base(s: &str) -> &'static Type {
-    match s.trim() {
-        "bool" => &BOOL,
-        "void" => &VOID,
+    match s {
         "float16_t" => &F16,
         "float16x4_t" => &F16X4,
         "float16x4x2_t" => &F16X4X2,
@@ -828,49 +739,6 @@ fn parse_ty_base(s: &str) -> &'static Type {
         "uint8x8x2_t" => &U8X8X2,
         "uint8x8x3_t" => &U8X8X3,
         "uint8x8x4_t" => &U8X8X4,
-        "svbool_t" => &SVBOOL,
-        "svfloat32_t" => &SVF32,
-        "svfloat32x2_t" => &SVF32X2,
-        "svfloat32x3_t" => &SVF32X3,
-        "svfloat32x4_t" => &SVF32X4,
-        "svfloat64_t" => &SVF64,
-        "svfloat64x2_t" => &SVF64X2,
-        "svfloat64x3_t" => &SVF64X3,
-        "svfloat64x4_t" => &SVF64X4,
-        "svint8_t" => &SVI8,
-        "svint8x2_t" => &SVI8X2,
-        "svint8x3_t" => &SVI8X3,
-        "svint8x4_t" => &SVI8X4,
-        "svint16_t" => &SVI16,
-        "svint16x2_t" => &SVI16X2,
-        "svint16x3_t" => &SVI16X3,
-        "svint16x4_t" => &SVI16X4,
-        "svint32_t" => &SVI32,
-        "svint32x2_t" => &SVI32X2,
-        "svint32x3_t" => &SVI32X3,
-        "svint32x4_t" => &SVI32X4,
-        "svint64_t" => &SVI64,
-        "svint64x2_t" => &SVI64X2,
-        "svint64x3_t" => &SVI64X3,
-        "svint64x4_t" => &SVI64X4,
-        "svuint8_t" => &SVU8,
-        "svuint8x2_t" => &SVU8X2,
-        "svuint8x3_t" => &SVU8X3,
-        "svuint8x4_t" => &SVU8X4,
-        "svuint16_t" => &SVU16,
-        "svuint16x2_t" => &SVU16X2,
-        "svuint16x3_t" => &SVU16X3,
-        "svuint16x4_t" => &SVU16X4,
-        "svuint32_t" => &SVU32,
-        "svuint32x2_t" => &SVU32X2,
-        "svuint32x3_t" => &SVU32X3,
-        "svuint32x4_t" => &SVU32X4,
-        "svuint64_t" => &SVU64,
-        "svuint64x2_t" => &SVU64X2,
-        "svuint64x3_t" => &SVU64X3,
-        "svuint64x4_t" => &SVU64X4,
-        "enum svprfop" => &SVPRFOP,
-        "enum svpattern" => &SVPATTERN,
 
         _ => panic!("failed to parse json type {s:?}"),
     }