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| author | Roy Buitenhuis <roy.buitenhuis@technolution.nl> | 2024-03-18 17:15:12 +0100 |
|---|---|---|
| committer | Roy Buitenhuis <roy.buitenhuis@technolution.nl> | 2024-03-20 16:02:10 +0100 |
| commit | 2fca27cd3b68bf8e883f1aeb0ae56fbf77ad2ef0 (patch) | |
| tree | 1f32062e9c267fb2eb7d8749ada9c22661148e24 /src/doc/rustc | |
| parent | c86f3ac24f6b62b438c4bdc34ae73e8a1db60234 (diff) | |
| download | rust-2fca27cd3b68bf8e883f1aeb0ae56fbf77ad2ef0.tar.gz rust-2fca27cd3b68bf8e883f1aeb0ae56fbf77ad2ef0.zip | |
Add bare metal riscv32 target.
Diffstat (limited to 'src/doc/rustc')
| -rw-r--r-- | src/doc/rustc/src/platform-support.md | 1 | ||||
| -rw-r--r-- | src/doc/rustc/src/platform-support/riscv32-unknown-none-elf.md | 6 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md index 274745b9082..75d38dd20bd 100644 --- a/src/doc/rustc/src/platform-support.md +++ b/src/doc/rustc/src/platform-support.md @@ -339,6 +339,7 @@ target | std | host | notes `riscv32gc-unknown-linux-gnu` | | | RISC-V Linux (kernel 5.4, glibc 2.33) `riscv32gc-unknown-linux-musl` | | | RISC-V Linux (kernel 5.4, musl 1.2.3 + RISCV32 support patches) [`riscv32im-risc0-zkvm-elf`](platform-support/riscv32im-risc0-zkvm-elf.md) | ? | | RISC Zero's zero-knowledge Virtual Machine (RV32IM ISA) +[`riscv32ima-unknown-none-elf`](platform-support/riscv32-unknown-none-elf.md) | * | | Bare RISC-V (RV32IMA ISA) [`riscv32imac-unknown-xous-elf`](platform-support/riscv32imac-unknown-xous-elf.md) | ? | | RISC-V Xous (RV32IMAC ISA) [`riscv32imc-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF [`riscv32imac-esp-espidf`](platform-support/esp-idf.md) | ✓ | | RISC-V ESP-IDF diff --git a/src/doc/rustc/src/platform-support/riscv32-unknown-none-elf.md b/src/doc/rustc/src/platform-support/riscv32-unknown-none-elf.md index 739b12bad8b..9a27a568b57 100644 --- a/src/doc/rustc/src/platform-support/riscv32-unknown-none-elf.md +++ b/src/doc/rustc/src/platform-support/riscv32-unknown-none-elf.md @@ -1,9 +1,13 @@ -# `riscv32{i,im,imc,imac,imafc}-unknown-none-elf` +# `riscv32{i,im,ima,imc,imac,imafc}-unknown-none-elf` **Tier: 2** Bare-metal target for RISC-V CPUs with the RV32I, RV32IM, RV32IMC, RV32IMAFC and RV32IMAC ISAs. +**Tier: 3** + +Bare-metal target for RISC-V CPUs with the RV32IMA ISA. + ## Target maintainers * Rust Embedded Working Group, [RISC-V team](https://github.com/rust-embedded/wg#the-risc-v-team) |