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authorJonathan 'theJPster' Pallant <github@thejpster.org.uk>2024-10-11 13:55:17 +0200
committerJonathan 'theJPster' Pallant <github@thejpster.org.uk>2024-10-11 13:55:17 +0200
commit5cc1c7b594d97245d2feffbe14478b15f4e48db8 (patch)
tree64d7f7a33a0c9cdadfae4c4844e8831f078f65f6 /src/doc/rustc
parentb52941dec76656f9c80c5f67e5326fafd256b9e0 (diff)
downloadrust-5cc1c7b594d97245d2feffbe14478b15f4e48db8.tar.gz
rust-5cc1c7b594d97245d2feffbe14478b15f4e48db8.zip
Note Integer MVE hard-float use-case in arm platform docs.
Diffstat (limited to 'src/doc/rustc')
-rw-r--r--src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md
index 40b19364f61..82fdc5b21cf 100644
--- a/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md
+++ b/src/doc/rustc/src/platform-support/thumbv8m.main-none-eabi.md
@@ -74,6 +74,11 @@ to use these flags.
 | Cortex-M85  | DP  | Yes | Int       | `cortex-m85`  | `-mve.fp`             |
 | Cortex-M85  | DP  | Yes | Int+Float | `cortex-m85`  | None                  |
 
+*Technically* you can use this hard-float ABI on a CPU which has no FPU but does
+have Integer MVE, because MVE provides the same set of registers as the FPU
+(including `s0` and `d0`). The particular set of flags that might enable this
+unusual scenario are currently not recorded here.
+
 <div class="warning">
 
 Never use the `-fpregs` *target-feature* with the `thumbv8m.main-none-eabihf`