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authorMark Rousskov <mark.simulacrum@gmail.com>2018-08-04 16:24:39 -0600
committerMark Rousskov <mark.simulacrum@gmail.com>2018-09-04 13:22:08 -0600
commit9ec5ef541ad17986bfe6ae067a84ea8f7b7ae133 (patch)
treeb66ab3ff4520b7abc1ea542ab3447c6d15e9047d /src/liballoc
parent1c2e17f4e3a2070a7f703f51e29c1c388ef703b6 (diff)
downloadrust-9ec5ef541ad17986bfe6ae067a84ea8f7b7ae133.tar.gz
rust-9ec5ef541ad17986bfe6ae067a84ea8f7b7ae133.zip
Breaking change upgrades
Diffstat (limited to 'src/liballoc')
-rw-r--r--src/liballoc/Cargo.toml2
-rw-r--r--src/liballoc/collections/linked_list.rs2
-rw-r--r--src/liballoc/tests/slice.rs5
3 files changed, 5 insertions, 4 deletions
diff --git a/src/liballoc/Cargo.toml b/src/liballoc/Cargo.toml
index 1dad323769a..642a43d4d9c 100644
--- a/src/liballoc/Cargo.toml
+++ b/src/liballoc/Cargo.toml
@@ -14,7 +14,7 @@ core = { path = "../libcore" }
 compiler_builtins = { path = "../rustc/compiler_builtins_shim" }
 
 [dev-dependencies]
-rand = "0.4"
+rand = "0.5"
 
 [[test]]
 name = "collectionstests"
diff --git a/src/liballoc/collections/linked_list.rs b/src/liballoc/collections/linked_list.rs
index 9844de9a57d..2ef84dbade0 100644
--- a/src/liballoc/collections/linked_list.rs
+++ b/src/liballoc/collections/linked_list.rs
@@ -1222,7 +1222,7 @@ mod tests {
     use std::thread;
     use std::vec::Vec;
 
-    use rand::{thread_rng, Rng};
+    use rand::{thread_rng, RngCore};
 
     use super::{LinkedList, Node};
 
diff --git a/src/liballoc/tests/slice.rs b/src/liballoc/tests/slice.rs
index df5e18a9a18..f33bf64d40b 100644
--- a/src/liballoc/tests/slice.rs
+++ b/src/liballoc/tests/slice.rs
@@ -18,7 +18,8 @@ use std::sync::atomic::Ordering::Relaxed;
 use std::sync::atomic::{ATOMIC_USIZE_INIT, AtomicUsize};
 use std::thread;
 
-use rand::{Rng, thread_rng};
+use rand::{Rng, RngCore, thread_rng};
+use rand::distributions::Standard;
 
 fn square(n: usize) -> usize {
     n * n
@@ -405,7 +406,7 @@ fn test_sort() {
     for len in (2..25).chain(500..510) {
         for &modulus in &[5, 10, 100, 1000] {
             for _ in 0..10 {
-                let orig: Vec<_> = rng.gen_iter::<i32>()
+                let orig: Vec<_> = rng.sample_iter::<i32, _>(&Standard)
                     .map(|x| x % modulus)
                     .take(len)
                     .collect();