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| author | Manish Goregaokar <manishsmail@gmail.com> | 2020-06-26 00:39:06 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-26 00:39:06 -0700 |
| commit | 81d2d3cf35127632927559c4eb78cfd17ff41c17 (patch) | |
| tree | 544c6f17dc79c71dca6cfa4f3696ba3df48eb342 /src/librustc_codegen_llvm | |
| parent | 25671fa0fc70a172e4d441916549b162023e8919 (diff) | |
| parent | a98868dc9f1d8654b615015144c9ff7310ba6e19 (diff) | |
| download | rust-81d2d3cf35127632927559c4eb78cfd17ff41c17.tar.gz rust-81d2d3cf35127632927559c4eb78cfd17ff41c17.zip | |
Rollup merge of #73588 - Amanieu:thumb-fp, r=nagisa
Fix handling of reserved registers for ARM inline asm `r6` is now disallowed as an operand since LLVM sometimes uses it as a base pointer. The check against using the frame pointer as an operand now takes the platform into account and will block either `r7` or `r11` as appropriate. Fixes #73450 cc @cbiffle
Diffstat (limited to 'src/librustc_codegen_llvm')
| -rw-r--r-- | src/librustc_codegen_llvm/llvm_util.rs | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/librustc_codegen_llvm/llvm_util.rs b/src/librustc_codegen_llvm/llvm_util.rs index 67a2251e859..80278bb9f53 100644 --- a/src/librustc_codegen_llvm/llvm_util.rs +++ b/src/librustc_codegen_llvm/llvm_util.rs @@ -156,6 +156,10 @@ const ARM_WHITELIST: &[(&str, Option<Symbol>)] = &[ ("vfp2", Some(sym::arm_target_feature)), ("vfp3", Some(sym::arm_target_feature)), ("vfp4", Some(sym::arm_target_feature)), + // This is needed for inline assembly, but shouldn't be stabilized as-is + // since it should be enabled per-function using #[instruction_set], not + // #[target_feature]. + ("thumb-mode", Some(sym::arm_target_feature)), ]; const AARCH64_WHITELIST: &[(&str, Option<Symbol>)] = &[ |