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| author | Amanieu d'Antras <amanieu@gmail.com> | 2020-06-21 15:34:18 +0100 |
|---|---|---|
| committer | Amanieu d'Antras <amanieu@gmail.com> | 2020-06-21 20:10:19 +0100 |
| commit | 8d0e8820659fdf8473f7ff8f2fe0d234d16965d7 (patch) | |
| tree | baede91eed4a2c747954540a0222c93e41e02e3f /src/librustc_codegen_llvm | |
| parent | 7adbc0dfeffcb6c2ae489cc97d28f76612c7cdf3 (diff) | |
| download | rust-8d0e8820659fdf8473f7ff8f2fe0d234d16965d7.tar.gz rust-8d0e8820659fdf8473f7ff8f2fe0d234d16965d7.zip | |
Fix handling of reserved registers for ARM inline asm
Diffstat (limited to 'src/librustc_codegen_llvm')
| -rw-r--r-- | src/librustc_codegen_llvm/llvm_util.rs | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/librustc_codegen_llvm/llvm_util.rs b/src/librustc_codegen_llvm/llvm_util.rs index 67a2251e859..80278bb9f53 100644 --- a/src/librustc_codegen_llvm/llvm_util.rs +++ b/src/librustc_codegen_llvm/llvm_util.rs @@ -156,6 +156,10 @@ const ARM_WHITELIST: &[(&str, Option<Symbol>)] = &[ ("vfp2", Some(sym::arm_target_feature)), ("vfp3", Some(sym::arm_target_feature)), ("vfp4", Some(sym::arm_target_feature)), + // This is needed for inline assembly, but shouldn't be stabilized as-is + // since it should be enabled per-function using #[instruction_set], not + // #[target_feature]. + ("thumb-mode", Some(sym::arm_target_feature)), ]; const AARCH64_WHITELIST: &[(&str, Option<Symbol>)] = &[ |