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authorRalf Jung <post@ralfj.de>2020-06-21 18:22:30 +0200
committerRalf Jung <post@ralfj.de>2020-06-21 18:22:30 +0200
commit3bfd0c9f0725b8fb096ea38446b4dcc2a3f90980 (patch)
tree219a687f01d1bef28ae44afcd82b648adaeffe1d /src/librustc_mir
parent38bd83df88288f2f8d1fc2dd317189cac3825920 (diff)
downloadrust-3bfd0c9f0725b8fb096ea38446b4dcc2a3f90980.tar.gz
rust-3bfd0c9f0725b8fb096ea38446b4dcc2a3f90980.zip
remove switch_ty reliance in codegen
Diffstat (limited to 'src/librustc_mir')
-rw-r--r--src/librustc_mir/interpret/terminator.rs5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/librustc_mir/interpret/terminator.rs b/src/librustc_mir/interpret/terminator.rs
index 1d57fce3973..a3cb450ff28 100644
--- a/src/librustc_mir/interpret/terminator.rs
+++ b/src/librustc_mir/interpret/terminator.rs
@@ -24,9 +24,10 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> {
 
             Goto { target } => self.go_to_block(target),
 
-            SwitchInt { ref discr, ref values, ref targets, .. } => {
+            SwitchInt { ref discr, ref values, ref targets, switch_ty } => {
                 let discr = self.read_immediate(self.eval_operand(discr, None)?)?;
                 trace!("SwitchInt({:?})", *discr);
+                assert_eq!(discr.layout.ty, switch_ty);
 
                 // Branch to the `otherwise` case by default, if no match is found.
                 assert!(!targets.is_empty());
@@ -55,7 +56,7 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> {
                 ref args,
                 destination,
                 ref cleanup,
-                from_hir_call: _from_hir_call,
+                from_hir_call: _,
                 fn_span: _,
             } => {
                 let old_stack = self.frame_idx();