Rollup merge of #48874 - jcowgill:mips-features, r=sanxiyn

bump mipsel isa leval and enable fpxx

This PR:
* Bumps the default ISA level of the mipsel targets to `mips32r2`. The big endian mips targets are already built with `mips32r2`. This is the usual baseline for the MIPS ISA these days used by other projects, although it does drop support for the 4K processor (which was the only processor released with mips32 r1). Debian no longer supports pre-R2 processors. Using R2 also improves code generation in FPXX in certain circumstances.
* Enables the FPXX floating point ABI[1] on 32-bit hard-float targets by default. This ABI adds some extra restrictions to the existing ABI which allows code to run on the two main floating point modes found on MIPS (FR0 and FR1) and remains compatible with the FR32 ABI currently in use. All code within an executable (including all shared libraries) must be compiled with FPXX/FP64 to be able to use MSA on 32-bit MIPS.
* Enables the "nooddspreg" feature with FPXX. This feature is usually enabled whenever FPXX is. It also helps workaround some issues on Loongson processors. I'm hoping this will fix some test failures mentioned in #39013.
* Adds the `fp64` feature to the MIPS whitelist. This feature must be enabled to use MSA on 32-bit MIPS, otherwise LLVM will complain.

[1] See https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking

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