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authorEduardo Sánchez Muñoz <esm@eduardosm.net>2020-07-02 13:47:19 +0200
committerEduardo Sánchez Muñoz <esm@eduardosm.net>2020-07-02 13:47:19 +0200
commit0f1adc8ec812df494df33640c1be147f35e5f6ac (patch)
tree5d1fe53539918232f1432a1d6ca35bbdeed4e8cc /src/libstd
parentaac2f734dec39a19e412b46fcdc0e67a6eafa3ad (diff)
downloadrust-0f1adc8ec812df494df33640c1be147f35e5f6ac.tar.gz
rust-0f1adc8ec812df494df33640c1be147f35e5f6ac.zip
Further improve comments in libstd/panicking.rs.
Diffstat (limited to 'src/libstd')
-rw-r--r--src/libstd/panicking.rs9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/libstd/panicking.rs b/src/libstd/panicking.rs
index 3a81b1f9a05..9542e7209b4 100644
--- a/src/libstd/panicking.rs
+++ b/src/libstd/panicking.rs
@@ -264,10 +264,11 @@ pub mod panic_count {
             // (including the current one) will have `LOCAL_PANIC_COUNT`
             // equal to zero, so TLS access can be avoided.
             //
-            // A relaxed atomic load is equivalent to a normal aligned memory read
-            // (e.g., a `mov` instruction in x86), while a TLS access might require
-            // calling a non-inlinable function (such as `__tls_get_addr` when using
-            // the GD TLS model).
+            // In terms of performance, a relaxed atomic load is similar to a normal
+            // aligned memory read (e.g., a mov instruction in x86), but with some
+            // compiler optimization restrictions. On the other hand, a TLS access
+            // might require calling a non-inlinable function (such as `__tls_get_addr`
+            // when using the GD TLS model).
             true
         } else {
             is_zero_slow_path()