diff options
| author | bors <bors@rust-lang.org> | 2015-02-27 05:21:05 +0000 |
|---|---|---|
| committer | bors <bors@rust-lang.org> | 2015-02-27 05:21:05 +0000 |
| commit | dd077d5decbc3e462a9fe2feb1a0af0486897acb (patch) | |
| tree | 162f7b0900f2e09f0b62c1fa04c2d1a226922524 /src/libstd | |
| parent | e5cd6534c1775531b4cfe374a5c81a5a2dd899b0 (diff) | |
| parent | c2400bb2690fe0ee1184d5d7a66b6d2d1198b480 (diff) | |
| download | rust-dd077d5decbc3e462a9fe2feb1a0af0486897acb.tar.gz rust-dd077d5decbc3e462a9fe2feb1a0af0486897acb.zip | |
Auto merge of #22857 - alexcrichton:net-flaky, r=alexcrichton
Instead of allocating the same ports for ipv4 and ipv6 tests, instead draw all ports from the same pool. Some tests connect to just "localhost" on a particular port which may accidentally be interacting with other tests as the ipv-what-ness isn't specified with the string "localhost" Relevant logs: * [Deadlock of the `net::tcp::tests::listen_localhost` test][mac] * [Failure of the `fast_rebind` test][win1] * [Failure of `multiple_connect_interleaved_lazy_schedule_ip4`][win2] [mac]: https://gist.github.com/alexcrichton/349c7ce7c620c1adb2f2 [win1]: https://gist.github.com/alexcrichton/7e3611faae2e1edaee6f [win2]: https://gist.github.com/alexcrichton/4f5f87749af3ad0f9851
Diffstat (limited to 'src/libstd')
| -rw-r--r-- | src/libstd/net/test.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/libstd/net/test.rs b/src/libstd/net/test.rs index aec50d638c6..dbebede9f50 100644 --- a/src/libstd/net/test.rs +++ b/src/libstd/net/test.rs @@ -14,14 +14,14 @@ use env; use net::{SocketAddr, IpAddr}; use sync::atomic::{AtomicUsize, ATOMIC_USIZE_INIT, Ordering}; +static PORT: AtomicUsize = ATOMIC_USIZE_INIT; + pub fn next_test_ip4() -> SocketAddr { - static PORT: AtomicUsize = ATOMIC_USIZE_INIT; SocketAddr::new(IpAddr::new_v4(127, 0, 0, 1), PORT.fetch_add(1, Ordering::SeqCst) as u16 + base_port()) } pub fn next_test_ip6() -> SocketAddr { - static PORT: AtomicUsize = ATOMIC_USIZE_INIT; SocketAddr::new(IpAddr::new_v6(0, 0, 0, 0, 0, 0, 0, 1), PORT.fetch_add(1, Ordering::SeqCst) as u16 + base_port()) } |
