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| author | Jorge Aparicio <japaricious@gmail.com> | 2016-09-15 20:46:04 -0500 |
|---|---|---|
| committer | Jorge Aparicio <japaricious@gmail.com> | 2016-10-02 15:52:26 -0500 |
| commit | 901c5f2aa4d2a473500e1daec8fd2f627ddde5d2 (patch) | |
| tree | a36762018c5f3220f4dec02ee43f7fcf9af6428f /src/test/run-pass/thinlto | |
| parent | 8991ffc3031b4e787f9216caa12aa556f5ede8ed (diff) | |
| download | rust-901c5f2aa4d2a473500e1daec8fd2f627ddde5d2.tar.gz rust-901c5f2aa4d2a473500e1daec8fd2f627ddde5d2.zip | |
add Thumbs to the compiler
this commit adds 4 new target definitions to the compiler for easier
cross compilation to ARM Cortex-M devices.
- `thumbv6m-none-eabi`
- For the Cortex-M0, Cortex-M0+ and Cortex-M1
- This architecture doesn't have hardware support (instructions) for
atomics. Hence, the `Atomic*` structs are not available for this
target.
- `thumbv7m-none-eabi`
- For the Cortex-M3
- `thumbv7em-none-eabi`
- For the FPU-less variants of the Cortex-M4 and Cortex-M7
- On this target, all the floating point operations will be lowered
software routines (intrinsics)
- `thumbv7em-none-eabihf`
- For the variants of the Cortex-M4 and Cortex-M7 that do have a FPU.
- On this target, all the floating point operations will be lowered
to hardware instructions
No binary releases of standard crates, like `core`, are planned for
these targets because Cargo, in the future, will compile e.g. the `core`
crate on the fly as part of the `cargo build` process. In the meantime,
you'll have to compile the `core` crate yourself. [Xargo] is the easiest
way to do that as in handles the compilation of `core` automatically and
can be used just like Cargo: `xargo build --target thumbv6m-none-eabi`
is all that's needed.
[Xargo]: https://crates.io/crates/xargo
Diffstat (limited to 'src/test/run-pass/thinlto')
0 files changed, 0 insertions, 0 deletions
