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| author | bjorn3 <17426603+bjorn3@users.noreply.github.com> | 2024-01-26 14:19:11 +0000 |
|---|---|---|
| committer | bjorn3 <17426603+bjorn3@users.noreply.github.com> | 2024-01-26 14:19:11 +0000 |
| commit | 604c8a7cf80eca33bd078d6b45faaa808ef9ecd8 (patch) | |
| tree | 91f0d41b6ed91ef0e0387f45d87dc46d31c4137e /src | |
| parent | dc7ed1680c093ea7667f841ecaa7b89f205aef6f (diff) | |
| download | rust-604c8a7cf80eca33bd078d6b45faaa808ef9ecd8.tar.gz rust-604c8a7cf80eca33bd078d6b45faaa808ef9ecd8.zip | |
Accept [u8; N] bitmasks in simd_select_bitmask
Fixes rust-lang/rustc_codegen_cranelift#1446
Diffstat (limited to 'src')
| -rw-r--r-- | src/intrinsics/simd.rs | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/src/intrinsics/simd.rs b/src/intrinsics/simd.rs index dfa54b775aa..ebdc744bcd8 100644 --- a/src/intrinsics/simd.rs +++ b/src/intrinsics/simd.rs @@ -822,7 +822,35 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>( let (lane_count, lane_ty) = a.layout().ty.simd_size_and_type(fx.tcx); let lane_layout = fx.layout_of(lane_ty); - let m = m.load_scalar(fx); + let expected_int_bits = lane_count.max(8); + let expected_bytes = expected_int_bits / 8 + ((expected_int_bits % 8 > 0) as u64); + + let m = match m.layout().ty.kind() { + ty::Uint(i) if i.bit_width() == Some(expected_int_bits) => m.load_scalar(fx), + ty::Array(elem, len) + if matches!(elem.kind(), ty::Uint(ty::UintTy::U8)) + && len.try_eval_target_usize(fx.tcx, ty::ParamEnv::reveal_all()) + == Some(expected_bytes) => + { + m.force_stack(fx).0.load( + fx, + Type::int(expected_int_bits as u16).unwrap(), + MemFlags::trusted(), + ) + } + _ => { + fx.tcx.dcx().span_fatal( + span, + format!( + "invalid monomorphization of `simd_select_bitmask` intrinsic: \ + cannot accept `{}` as mask, expected `u{}` or `[u8; {}]`", + ret.layout().ty, + expected_int_bits, + expected_bytes + ), + ); + } + }; for lane in 0..lane_count { let m_lane = fx.bcx.ins().ushr_imm(m, u64::from(lane) as i64); |
