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| author | Antoni Boucher <bouanto@zoho.com> | 2024-09-03 21:09:49 -0400 |
|---|---|---|
| committer | Antoni Boucher <bouanto@zoho.com> | 2024-09-03 21:09:49 -0400 |
| commit | 623dc09fa3a1d12f5a83ed763f4defa1c7e84c67 (patch) | |
| tree | 02b5db8e2d3f2c30625caf03ad7f0beca79e522b /src | |
| parent | 39e191077bb075a1b4f6facc9b75e5270cb507e4 (diff) | |
| download | rust-623dc09fa3a1d12f5a83ed763f4defa1c7e84c67.tar.gz rust-623dc09fa3a1d12f5a83ed763f4defa1c7e84c67.zip | |
Add support for more SIMD intrinsics
Diffstat (limited to 'src')
| -rw-r--r-- | src/intrinsic/llvm.rs | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index 286aa6dab75..ba57e425b0f 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -501,7 +501,8 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>( } "__builtin_ia32_rangesd128_mask_round" | "__builtin_ia32_rangess128_mask_round" - | "__builtin_ia32_reducesd_mask_round" => { + | "__builtin_ia32_reducesd_mask_round" + | "__builtin_ia32_reducess_mask_round" => { let new_args = args.to_vec(); args = vec![ new_args[0], @@ -1061,6 +1062,21 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.mask.reduce.pd.512" => "__builtin_ia32_reducepd512_mask_round", "llvm.x86.avx512.mask.reduce.ps.512" => "__builtin_ia32_reduceps512_mask_round", "llvm.x86.avx512.mask.reduce.sd" => "__builtin_ia32_reducesd_mask_round", + "llvm.x86.avx512.mask.reduce.ss" => "__builtin_ia32_reducess_mask_round", + "llvm.x86.avx512.mask.loadu.d.256" => "__builtin_ia32_loaddqusi256_mask", + "llvm.x86.avx512.mask.loadu.q.256" => "__builtin_ia32_loaddqudi256_mask", + "llvm.x86.avx512.mask.loadu.ps.256" => "__builtin_ia32_loadups256_mask", + "llvm.x86.avx512.mask.loadu.pd.256" => "__builtin_ia32_loadupd256_mask", + "llvm.x86.avx512.mask.loadu.d.128" => "__builtin_ia32_loaddqusi128_mask", + "llvm.x86.avx512.mask.loadu.q.128" => "__builtin_ia32_loaddqudi128_mask", + "llvm.x86.avx512.mask.loadu.ps.128" => "__builtin_ia32_loadups128_mask", + "llvm.x86.avx512.mask.loadu.pd.128" => "__builtin_ia32_loadupd128_mask", + "llvm.x86.avx512.mask.load.d.512" => "__builtin_ia32_movdqa32load512_mask", + "llvm.x86.avx512.mask.load.q.512" => "__builtin_ia32_movdqa64load512_mask", + "llvm.x86.avx512.mask.load.ps.512" => "__builtin_ia32_loadaps512_mask", + "llvm.x86.avx512.mask.load.pd.512" => "__builtin_ia32_loadapd512_mask", + "llvm.x86.avx512.mask.load.d.256" => "__builtin_ia32_movdqa32load256_mask", + "llvm.x86.avx512.mask.load.q.256" => "__builtin_ia32_movdqa64load256_mask", // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py _ => include!("archs.rs"), |