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| author | bjorn3 <17426603+bjorn3@users.noreply.github.com> | 2024-06-02 11:18:51 +0200 |
|---|---|---|
| committer | bjorn3 <17426603+bjorn3@users.noreply.github.com> | 2024-06-02 11:19:47 +0200 |
| commit | 8f1d41e2a0cf73f6ecb1737f0c70a07bc8989bfa (patch) | |
| tree | 3ef6ac91914c4a085c6ee3ff90a131cb0a79718a /src | |
| parent | ab10da27a11133add161bc6f9b2b7580ba455d58 (diff) | |
| download | rust-8f1d41e2a0cf73f6ecb1737f0c70a07bc8989bfa.tar.gz rust-8f1d41e2a0cf73f6ecb1737f0c70a07bc8989bfa.zip | |
Implement _rdtsc x86 vendor intrinsic
Fixes rust-lang/rustc_codegen_cranelift#1493
Diffstat (limited to 'src')
| -rw-r--r-- | src/intrinsics/llvm_x86.rs | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/intrinsics/llvm_x86.rs b/src/intrinsics/llvm_x86.rs index 27b55ecc72e..03dca0656ef 100644 --- a/src/intrinsics/llvm_x86.rs +++ b/src/intrinsics/llvm_x86.rs @@ -1416,6 +1416,36 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>( ret.write_cvalue(fx, res); } + "llvm.x86.rdtsc" => { + // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_rdtsc&ig_expand=5273 + + let res_place = CPlace::new_stack_slot( + fx, + fx.layout_of(Ty::new_tup(fx.tcx, &[fx.tcx.types.u32, fx.tcx.types.u32])), + ); + let eax_place = res_place.place_field(fx, FieldIdx::new(0)); + let edx_place = res_place.place_field(fx, FieldIdx::new(1)); + codegen_inline_asm_inner( + fx, + &[InlineAsmTemplatePiece::String("rdtsc".to_string())], + &[ + CInlineAsmOperand::Out { + reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::ax)), + late: true, + place: Some(eax_place), + }, + CInlineAsmOperand::Out { + reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::dx)), + late: true, + place: Some(edx_place), + }, + ], + InlineAsmOptions::NOSTACK | InlineAsmOptions::NOMEM, + ); + let res = res_place.to_cvalue(fx); + ret.write_cvalue_transmute(fx, res); + } + _ => { fx.tcx .dcx() |
