Add initial asm!() support for PowerPC

This includes GPRs and FPRs only

2 files changed, 176 insertions, 1 deletions

diff --git a/src/doc/unstable-book/src/library-features/asm.md b/src/doc/unstable-book/src/library-features/asm.md
index fa96e47ee03..107fc6d42cf 100644
--- a/src/doc/unstable-book/src/library-features/asm.md
+++ b/src/doc/unstable-book/src/library-features/asm.md
@@ -26,6 +26,7 @@ Inline assembly is currently supported on the following architectures:
 - AArch64
 - RISC-V
 - NVPTX
+- PowerPC
 - Hexagon
 - MIPS32r2 and MIPS64r2
 - wasm32
@@ -459,7 +460,7 @@ options := "options(" option *["," option] [","] ")"
 asm := "asm!(" format_string *("," format_string) *("," [ident "="] operand) ["," options] [","] ")"
 ```
 
-The macro will initially be supported only on ARM, AArch64, Hexagon, x86, x86-64 and RISC-V targets. Support for more targets may be added in the future. The compiler will emit an error if `asm!` is used on an unsupported target.
+The macro will initially be supported only on ARM, AArch64, Hexagon, PowerPC, x86, x86-64 and RISC-V targets. Support for more targets may be added in the future. The compiler will emit an error if `asm!` is used on an unsupported target.
 
 [format-syntax]: https://doc.rust-lang.org/std/fmt/#syntax
 
@@ -565,6 +566,9 @@ Here is the list of currently supported register classes:
 | RISC-V | `reg` | `x1`, `x[5-7]`, `x[9-15]`, `x[16-31]` (non-RV32E) | `r` |
 | RISC-V | `freg` | `f[0-31]` | `f` |
 | Hexagon | `reg` | `r[0-28]` | `r` |
+| PowerPC | `reg` | `r[0-31]` | `r` |
+| PowerPC | `reg_nonzero` | | `r[1-31]` | `b` |
+| PowerPC | `freg` | `f[0-31]` | `f` |
 | wasm32 | `local` | None\* | `r` |
 
 > **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register.
@@ -607,6 +611,9 @@ Each register class has constraints on which value types they can be used with.
 | RISC-V | `freg` | `f` | `f32` |
 | RISC-V | `freg` | `d` | `f64` |
 | Hexagon | `reg` | None | `i8`, `i16`, `i32`, `f32` |
+| PowerPC | `reg` | None | `i8`, `i16`, `i32` |
+| PowerPC | `reg_nonzero` | None | `i8`, `i16`, `i32` |
+| PowerPC | `freg` | None | `f32`, `f64` |
 | wasm32 | `local` | None | `i8` `i16` `i32` `i64` `f32` `f64` |
 
 > **Note**: For the purposes of the above table pointers, function pointers and `isize`/`usize` are treated as the equivalent integer type (`i16`/`i32`/`i64` depending on the target).
@@ -744,6 +751,9 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
 | RISC-V | `reg` | None | `x1` | None |
 | RISC-V | `freg` | None | `f0` | None |
 | Hexagon | `reg` | None | `r0` | None |
+| PowerPC | `reg` | None | `0` | None |
+| PowerPC | `reg_nonzero` | None | `3` | `b` |
+| PowerPC | `freg` | None | `0` | None |
 
 > Notes:
 > - on ARM `e` / `f`: this prints the low or high doubleword register name of a NEON quad (128-bit) register.
diff --git a/src/test/assembly/asm/powerpc-types.rs b/src/test/assembly/asm/powerpc-types.rs
new file mode 100644
index 00000000000..26c891392f2
--- /dev/null
+++ b/src/test/assembly/asm/powerpc-types.rs
@@ -0,0 +1,165 @@
+// min-llvm-version: 10.0.1
+// assembly-output: emit-asm
+// compile-flags: --target powerpc-unknown-linux-gnu
+// needs-llvm-components: powerpc
+
+#![feature(no_core, lang_items, rustc_attrs, repr_simd)]
+#![crate_type = "rlib"]
+#![no_core]
+#![allow(asm_sub_register, non_camel_case_types)]
+
+#[rustc_builtin_macro]
+macro_rules! asm {
+    () => {};
+}
+#[rustc_builtin_macro]
+macro_rules! concat {
+    () => {};
+}
+#[rustc_builtin_macro]
+macro_rules! stringify {
+    () => {};
+}
+
+#[lang = "sized"]
+trait Sized {}
+#[lang = "copy"]
+trait Copy {}
+
+type ptr = *const i32;
+
+impl Copy for i8 {}
+impl Copy for u8 {}
+impl Copy for i16 {}
+impl Copy for i32 {}
+impl Copy for i64 {}
+impl Copy for f32 {}
+impl Copy for f64 {}
+impl Copy for ptr {}
+extern "C" {
+    fn extern_func();
+    static extern_static: u8;
+}
+
+// Hack to avoid function merging
+extern "Rust" {
+    fn dont_merge(s: &str);
+}
+
+macro_rules! check { ($func:ident, $ty:ty, $class:ident, $mov:literal) => {
+    #[no_mangle]
+    pub unsafe fn $func(x: $ty) -> $ty {
+        dont_merge(stringify!($func));
+
+        let y;
+        asm!(concat!($mov," {}, {}"), out($class) y, in($class) x);
+        y
+    }
+};}
+
+macro_rules! check_reg { ($func:ident, $ty:ty, $rego:tt, $regc:tt, $mov:literal) => {
+    #[no_mangle]
+    pub unsafe fn $func(x: $ty) -> $ty {
+        dont_merge(stringify!($func));
+
+        let y;
+        asm!(concat!($mov, " ", $rego, ", ", $rego), lateout($regc) y, in($regc) x);
+        y
+    }
+};}
+
+// CHECK-LABEL: reg_i8:
+// CHECK: #APP
+// CHECK: mr {{[0-9]+}}, {{[0-9]+}}
+// CHECK: #NO_APP
+check!(reg_i8, i8, reg, "mr");
+
+// CHECK-LABEL: reg_i16:
+// CHECK: #APP
+// CHECK: mr {{[0-9]+}}, {{[0-9]+}}
+// CHECK: #NO_APP
+check!(reg_i16, i16, reg, "mr");
+
+// CHECK-LABEL: reg_i32:
+// CHECK: #APP
+// CHECK: mr {{[0-9]+}}, {{[0-9]+}}
+// CHECK: #NO_APP
+check!(reg_i32, i32, reg, "mr");
+
+// CHECK-LABEL: reg_i8_nz:
+// CHECK: #APP
+// CHECK: mr {{[0-9]+}}, {{[0-9]+}}
+// CHECK: #NO_APP
+check!(reg_i8_nz, i8, reg_nonzero, "mr");
+
+// CHECK-LABEL: reg_i16_nz:
+// CHECK: #APP
+// CHECK: mr {{[0-9]+}}, {{[0-9]+}}
+// CHECK: #NO_APP
+check!(reg_i16_nz, i16, reg_nonzero, "mr");
+
+// CHECK-LABEL: reg_i32_nz:
+// CHECK: #APP
+// CHECK: mr {{[0-9]+}}, {{[0-9]+}}
+// CHECK: #NO_APP
+check!(reg_i32_nz, i32, reg_nonzero, "mr");
+
+// CHECK-LABEL: reg_f32:
+// CHECK: #APP
+// CHECK: fmr {{[0-9]+}}, {{[0-9]+}}
+// CHECK: #NO_APP
+check!(reg_f32, f32, freg, "fmr");
+
+// CHECK-LABEL: reg_f64:
+// CHECK: #APP
+// CHECK: fmr {{[0-9]+}}, {{[0-9]+}}
+// CHECK: #NO_APP
+check!(reg_f64, f64, freg, "fmr");
+
+// CHECK-LABEL: reg_i8_r0:
+// CHECK: #APP
+// CHECK: mr 0, 0
+// CHECK: #NO_APP
+check_reg!(reg_i8_r0, i8, "0", "0", "mr");
+
+// CHECK-LABEL: reg_i16_r0:
+// CHECK: #APP
+// CHECK: mr 0, 0
+// CHECK: #NO_APP
+check_reg!(reg_i16_r0, i16, "0", "0", "mr");
+
+// CHECK-LABEL: reg_i32_r0:
+// CHECK: #APP
+// CHECK: mr 0, 0
+// CHECK: #NO_APP
+check_reg!(reg_i32_r0, i32, "0", "0", "mr");
+
+// CHECK-LABEL: reg_i8_r18:
+// CHECK: #APP
+// CHECK: mr 18, 18
+// CHECK: #NO_APP
+check_reg!(reg_i8_r18, i8, "18", "18", "mr");
+
+// CHECK-LABEL: reg_i16_r18:
+// CHECK: #APP
+// CHECK: mr 18, 18
+// CHECK: #NO_APP
+check_reg!(reg_i16_r18, i16, "18", "18", "mr");
+
+// CHECK-LABEL: reg_i32_r18:
+// CHECK: #APP
+// CHECK: mr 18, 18
+// CHECK: #NO_APP
+check_reg!(reg_i32_r18, i32, "18", "18", "mr");
+
+// CHECK-LABEL: reg_f32_f0:
+// CHECK: #APP
+// CHECK: fmr 0, 0
+// CHECK: #NO_APP
+check_reg!(reg_f32_f0, f32, "0", "f0", "fmr");
+
+// CHECK-LABEL: reg_f64_f0:
+// CHECK: #APP
+// CHECK: fmr 0, 0
+// CHECK: #NO_APP
+check_reg!(reg_f64_f0, f64, "0", "f0", "fmr");